Multigate Source/Drain Contact Structure for Low Contact Resistivity
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Solution Overview
Problem
Parasitic resistance-capacitance (RC) delay has become a significant challenge in multigate devices as geometry sizes are reduced to achieve faster operating speeds, leading to increased source/drain contact resistance, which is not effectively addressed by current methods compatible with non-planar transistors.
Innovation Solution
A doped crystalline semiconductor layer, such as a gallium-doped germanium layer, is inserted between the source/drain feature and contact, formed by depositing a doped amorphous semiconductor layer and crystallizing it through annealing, without ion implantation or epitaxial growth, to reduce contact resistivity at the metal-semiconductor interface.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If current contact resistivity reduction methods are used, then source/drain contact resistance decreases, but device integrity is damaged due to high thermal budgets
Solution Approach 1:
The patent changes the thermal parameter from high temperature (conventional method) to low temperature (below 450°C) processing. This is achieved by using a doped amorphous semiconductor layer that can be deposited and annealed at low temperatures, fundamentally altering the thermal budget parameter to resolve the contradiction between reducing contact resistance and preventing device damage
Solution Approach 2:
The patent introduces a composite structure consisting of a doped amorphous semiconductor layer (such as gallium-doped amorphous germanium) between the metal contact and the source/drain region. This composite material approach enables effective contact resistance reduction while maintaining device integrity, as the amorphous layer can be processed at low temperatures unlike conventional crystalline semiconductor methods
2Speed
If scaling is continued to improve device performance, then operating speed increases, but parasitic RC delay becomes significant
Solution Approach 1:
The patent changes the contact resistivity parameter by introducing a specially doped amorphous semiconductor layer. This layer provides optimized electrical properties that reduce parasitic resistance, counteracting the increasing RC delay effects that arise from continued device scaling and enabling faster operating speeds without sacrificing performance
3Productivity
If source/drain contact size is decreased to enable scaling, then device density increases, but source/drain contact resistance increases
Solution Approach 1:
The patent applies local quality by creating a doped amorphous semiconductor layer specifically at the contact interface region. This localized doping approach concentrates the beneficial electrical properties exactly where needed (at the metal-semiconductor interface) without requiring overall enlargement of the contact structure, thus maintaining high device density while reducing contact resistance
Solution Approach 2:
The patent uses a composite material system where a doped amorphous semiconductor layer is combined with the metal contact and underlying source/drain region. This composite structure provides superior electrical contact properties that compensate for the reduced contact size, enabling both high device density and low contact resistance to coexist
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces contact resistivity to less than 1×10−9Ω-cm2, improving performance while being compatible with conventional multigate device fabrication and avoiding damage from high thermal processes.
Implementation Method 1
performing an annealing process to crystallize at least portions of the doped amorphous semiconductor layer that wrap the source/drain feature, thereby forming a doped crystalline semiconductor layer
Data Source
AI summary
An exemplary method includes forming an opening in an interlevel dielectric (ILD) layer. The opening in the ILD layer exposes a doped epitaxial layer. The method further includes performing an in-situ doping deposition process, an annealing process, and an etching process to form a doped semiconductor layer over the doped epitaxial layer. The doped semiconductor layer partially fills the opening. The method further includes forming a metal-comprising structure that fills a remainder of the opening. The metal-comprising structure is disposed over a top and sidewalls of the doped epitaxial layer. The doped semiconductor layer is disposed between the metal-comprising structure and the top of the doped epitaxial layer and between the metal-comprising structure and the sidewalls of the doped epitaxial layer. The in-situ deposition process may implement a temperature less than about 350° C. The doped epitaxial layer includes p-type dopant (e.g., boron), and the doped semiconductor layer includes gallium.