Multi-Gate Gate Stack Convex Sidewalls for Reliable GAA Transistors
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Solution Overview
Problem
Existing multi-gate semiconductor devices, such as GAA transistors, face challenges with degraded metal gate-to-source/drain reliability and poor high-K dielectric deposition due to concave sidewall profiles in the metal gate layer, leading to increased complexity and reliability issues.
Innovation Solution
Implementing a convex sidewall profile for the metal gate layer during the SiGe recess process, utilizing a high/low Ge concentration bi-layer epitaxial layer to achieve different etching rates, which enhances the inner spacer/metal gate layer interface and improves high-K dielectric deposition.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a conventional metal gate layer with concave sidewall profile is used in GAA transistors, then the device can be fabricated using standard processes, but the metal gate-to-source/drain reliability is degraded and high-K dielectric deposition is poor
Solution Approach 1:
The patent inverts the conventional concave sidewall profile to a convex sidewall profile for the metal gate layer. This inversion is achieved by controlling the etching process to create outward-curving sidewalls instead of inward-curving ones, thereby improving metal gate-to-source/drain reliability and high-K dielectric deposition quality.
Solution Approach 2:
The patent changes the geometric parameters of the metal gate layer by forming a convex sidewall profile with specific curvature characteristics. This parameter change optimizes the interface geometry between the metal gate and source/drain regions, leading to improved reliability and deposition properties.
2Productivity
If GAA transistor fabrication is implemented to meet performance requirements beyond FinFET capabilities, then device performance is improved, but manufacturing process complexity and device reliability concerns increase
Solution Approach 1:
The patent modifies the sidewall profile parameter of the metal gate layer from concave to convex, which simplifies the deposition process for high-K dielectrics and improves overall manufacturing feasibility while maintaining the advanced performance benefits of GAA transistors.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The convex sidewall profile addresses reliability issues and improves dielectric deposition, resulting in enhanced device performance and reduced manufacturing complexity for multi-gate devices.
Implementation Method 1
utilizing a high/low Ge concentration bi-layer epitaxial layer to achieve different etching rates
Implementation Method 2
enhances the inner spacer/metal gate layer interface
Implementation Method 3
improves high-K dielectric deposition
Data Source
AI summary
A method of fabricating a device includes providing a fin having a plurality of channel layers and a plurality of multilayer epitaxial layers interposing the plurality of channel layers. The multilayer epitaxial layers include a first epitaxial layer interposed between second and third epitaxial layers. The first epitaxial layer has a first etch rate and the second and third epitaxial layers have a second etch rate greater than the first etch rate. The method further includes laterally etching the first, second, and third epitaxial layers to provide a convex sidewall profile on opposing lateral surfaces of the multilayer epitaxial layers. The method further includes forming an inner spacer between adjacent channel layers. The inner spacer interfaces the convex sidewall profile of the multilayer epitaxial layers along a first inner spacer sidewall surface. The method further includes replacing the multilayer epitaxial layers with a portion of a gate structure.