Multi-Gate Source/Drain Doping Gradient for Leakage Control
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing GAA transistor fabrication faces challenges due to suboptimal doping of source/drain features, leading to issues such as high sub-threshold leakage, unbalanced pass-gate/pull-up threshold voltages, and increased parasitic capacitance, which affect the performance and yield of SRAM devices.
Innovation Solution
Implementing a dopant gradient within the source/drain epitaxial features of GAA transistors, where a first layer suppresses leakage and prevents dopant out-diffusion, and a second layer reduces contact resistance, with specific doping profiles for different regions to enhance performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional doping methods are used in GAA transistor fabrication, then manufacturing process simplicity is maintained, but sub-threshold leakage increases and short-channel control deteriorates
Solution Approach 1:
The source/drain region is divided into multiple epitaxial layers with different doping concentrations. The first epitaxial layer has a first doping concentration and the second epitaxial layer has a second doping concentration, creating a graded doping profile that improves short-channel control while managing process complexity through systematic layering
Solution Approach 2:
Different regions of the source/drain structure are doped with different concentrations tailored to their specific functional requirements. The first epitaxial layer is doped to suppress leakage, while the second epitaxial layer is doped to reduce contact resistance, optimizing local properties for different operational needs
2Reliability
If source/drain regions are heavily doped to reduce contact resistance, then contact resistance decreases, but dopant out-diffusion increases and threshold voltage balance is disrupted
Solution Approach 1:
The first epitaxial layer with its specific doping concentration is formed in advance to suppress dopant out-diffusion before the second epitaxial layer is deposited. This preliminary doping structure acts as a barrier that prevents excessive dopant migration during subsequent processing steps
Solution Approach 2:
The doping concentration is locally optimized for each epitaxial layer. The first layer has a doping concentration optimized for preventing out-diffusion, while the second layer has a doping concentration optimized for reducing contact resistance, allowing each region to perform its specific function without compromising the other
3Reliability
If uniform doping is applied to all source/drain regions, then manufacturing simplicity is maintained, but pass-gate and pull-up threshold voltages become unbalanced
Solution Approach 1:
Different doping concentrations are applied to different epitaxial layers based on their specific functional requirements. The first epitaxial layer is doped to achieve desired threshold voltage characteristics, while the second epitaxial layer is doped to optimize contact properties, creating local optimization without requiring completely different processing for each region
Solution Approach 2:
The source/drain structure is segmented into multiple epitaxial layers that can be doped independently. This segmentation allows the pass-gate and pull-up regions to have different doping profiles tailored to their specific threshold voltage requirements, achieving balance through structured differentiation rather than uniform treatment
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The dopant gradient improves short-channel control, reduces sub-threshold leakage, and enhances SRAM cell yield and operation margin by balancing threshold voltages, resulting in improved performance and reliability.
Implementation Method 1
Implementing a dopant gradient within the source/drain epitaxial features of GAA transistors, where a first layer suppresses leakage and prevents dopant out-diffusion
Data Source
AI summary
A method of fabricating a device includes providing a fin element in a device region and forming a dummy gate over the fin element. In some embodiments, the method further includes forming a source/drain feature within a source/drain region adjacent to the dummy gate. In some cases, the source/drain feature includes a bottom region and a top region contacting the bottom region at an interface interposing the top and bottom regions. In some embodiments, the method further includes performing a plurality of dopant implants into the source/drain feature. In some examples, the plurality of dopant implants includes implantation of a first dopant within the bottom region and implantation of a second dopant within the top region. In some embodiments, the first dopant has a first graded doping profile within the bottom region, and the second dopant has a second graded doping profile within the top region.