Multi-Gate Transistor Gate Via Structure for Controlled Etching
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Solution Overview
Problem
In the fabrication of integrated circuits, particularly for transistors like FinFETs and GAA devices, there is a challenge in preventing over-etching of dielectric materials during the formation of source/drain vias, which can lead to increased leakage current and reduced device performance due to the lack of effective etch stop layers.
Innovation Solution
The introduction of a selectively formed etch stop layer (ESL) with different etch selectivity than the interlayer dielectric (ILD) layer, which slows down or stops the etching process, preventing over-etching and ensuring precise formation of via openings and source/drain vias without overlapping the source/drain contacts.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If the etching process is performed to form source/drain vias, then the via openings are created, but over-etching of dielectric materials occurs leading to increased leakage current
Solution Approach 1:
An etch stop layer is formed over the source/drain contacts before the via etching process. This preliminary action creates a protective barrier that prevents over-etching of the dielectric materials, thereby eliminating the harmful leakage current while maintaining precise via opening formation.
Solution Approach 2:
The etch stop layer acts as an intermediary element between the source/drain contacts and the dielectric materials. It mediates the etching process by being selectively removed to expose the contacts while protecting the surrounding dielectric structures from damage, thus preventing leakage current.
2Productivity
If the etching process is performed without etch stop layers, then the via openings can be formed, but the device performance is reduced due to over-etching
Solution Approach 1:
The etch stop layer is formed in advance over the source/drain contacts before the via etching process begins. This preliminary protective measure enables efficient via formation while simultaneously protecting device performance by preventing over-etching damage to the dielectric materials.
3Manufacturing precision
If the etching process continues without interruption, then the via openings are completed, but the source/drain contacts may be exposed or damaged
Solution Approach 1:
The etch stop layer serves as an intermediary protective barrier over the source/drain contacts during the via etching process. It is selectively removed to expose the contacts for via formation while protecting the contacts from damage, ensuring both manufacturing precision and contact integrity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces the risk of leakage current and improves the resistance-capacitance (RC) delay by maintaining a controlled etching process, allowing for more precise and reliable formation of source/drain vias, thereby enhancing the overall performance and reliability of the integrated circuit transistors.
Implementation Method 1
selectively formed etch stop layer (ESL) with different etch selectivity than the interlayer dielectric (ILD) layer, which slows down or stops the etching process
Data Source
AI summary
A method includes forming a gate structure over a substrate. A dielectric cap is formed over the gate structure. An etch stop layer is deposited over the dielectric cap. An interlayer dielectric (ILD) layer is deposited over the etch stop layer. The ILD layer is in contact with a sidewall of the etch stop layer. A gate via in the ILD layer is formed to pass through the etch stop layer and the dielectric cap to the gate structure.