Multi-Gate Inner Spacer Structure With Air Gaps for Low Capacitance
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Solution Overview
Problem
Existing inner spacer features in multi-gate transistors, such as MBC transistors, provide adequate etch resistance but lead to high parasitic capacitance due to their high dielectric constant, degrading device performance.
Innovation Solution
Incorporating a dielectric layer with air gaps in the inner spacer features to reduce parasitic capacitance by using a combination of dielectric material and air gaps, which are formed during the fabrication process to isolate the gate structure from the source/drain features.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If inner spacer features are formed of etch resistant dielectric material, then etch resistance is improved, but parasitic capacitance increases due to high dielectric constant
Solution Approach 1:
The inner spacer feature is formed as a composite structure comprising a first dielectric material layer (providing etch resistance) and a second dielectric material layer with air gaps (providing low parasitic capacitance). This composite approach allows simultaneous achievement of etch resistance and low parasitic capacitance by combining materials with complementary properties.
Solution Approach 2:
The second dielectric material layer incorporates air gaps creating a porous structure that significantly reduces the effective dielectric constant. This porous configuration maintains the spacing function while minimizing parasitic capacitance between the gate structure and source/drain features.
2Strength
If inner spacer features use high dielectric constant material for etch protection, then protection during etching is improved, but electrical performance degrades due to increased capacitance
Solution Approach 1:
The inner spacer feature is segmented into two distinct functional layers: the first dielectric material layer dedicated to etch protection, and the second dielectric material layer with air gaps dedicated to electrical performance. This segmentation allows each layer to optimize its specific function without compromising the other.
Solution Approach 2:
Different regions of the inner spacer feature have different material properties optimized for their local function. The portion adjacent to the gate structure uses low-k material with air gaps to minimize capacitance, while maintaining sufficient etch resistance through the composite structure.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The integration of air gaps in the inner spacer features significantly reduces parasitic capacitance, enhancing the performance of multi-gate transistors by minimizing electrical interference and maintaining etch resistance.
Implementation Method 1
the high dielectric constant may lead to a high parasitic capacitance between the gate structure and the source/drain feature
Implementation Method 2
the inner spacer features may be formed of an etch resistant dielectric material that tends to have a high dielectric constant
Data Source
AI summary
A semiconductor device and a method of forming the same are provided. In an embodiment, an exemplary semiconductor device includes a vertical stack of channel members disposed over a substrate, a gate structure wrapping around each channel member of the vertical stack of channel members, and a source/drain feature disposed over the substrate and coupled to the vertical stack of channel members. The source/drain feature is spaced apart from a sidewall of the gate structure by an air gap and a dielectric layer, and the air gap extends into the source/drain feature.