Multigate Source-Drain Engineering With Airgaps for Lower Contact Resistance
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Solution Overview
Problem
The challenge in the integrated circuit (IC) industry is to maintain gate control and reduce parasitic capacitance and contact resistance while scaling down IC technologies, as existing multigate devices face issues like increased parasitic capacitance, contact resistance, and short channel effects.
Innovation Solution
The method involves fabricating multigate devices with p-type and n-type GAA transistors, utilizing a specific semiconductor layer stack configuration, epitaxial source/drain features with bar-like or lollipop-like profiles, and airgaps to reduce parasitic capacitance and contact resistance, along with a detailed fabrication process that includes forming semiconductor fins, gate structures, and epitaxial growth to optimize device performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Object-generated harmful factors
If conventional fabrication technologies are used for multigate devices, then manufacturing process simplicity is maintained, but parasitic capacitance and contact resistance increase
Solution Approach 1:
The source/drain region is segmented into multiple discrete features (first source/drain feature, second source/drain feature) separated by airgaps, rather than forming a continuous source/drain structure. This segmentation reduces parasitic capacitance between source and drain by introducing low-dielectric constant air regions between the conductive features.
Solution Approach 2:
Airgaps are introduced as intermediary regions between the source/drain features and between source/drain features and fins. These air regions act as mediators with low dielectric constant properties that reduce parasitic capacitance while allowing the fabrication process to proceed with conventional techniques for forming the features themselves.
2Object-generated harmful factors
If conventional source/drain structures are used, then manufacturing simplicity is maintained, but contact resistance increases
Solution Approach 1:
Different regions of the source/drain structure are given different properties: the source/drain features have high conductivity for low contact resistance, while the airgaps between them have low dielectric constant for reduced parasitic capacitance. This local differentiation optimizes both contact resistance and parasitic capacitance in their respective regions.
Solution Approach 2:
The source/drain structure transitions from a conventional two-dimensional planar configuration to a three-dimensional vertical structure with multiple source/drain features stacked or positioned in space with airgaps. This dimensional change increases the effective contact area while maintaining reduced parasitic capacitance through the airgap separation.
3Length of moving object
If scaling is continued to improve device performance, then IC dimensions are reduced, but short-channel effects increase
Solution Approach 1:
The channel region is segmented into multiple fins surrounded by gate structures, creating multiple parallel current paths. This segmentation allows the device to scale to smaller dimensions while maintaining good gate control over each individual fin, thereby reducing short-channel effects that would otherwise dominate in scaled devices.
Solution Approach 2:
The gate structure is nested around the fin channels in a gate-all-around configuration, with multiple fins nested within the gate structure. This nested arrangement provides maximum gate control over the channel region at scaled dimensions, effectively suppressing short-channel effects while allowing continued scaling.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively reduces parasitic capacitance and contact resistance, enhancing the performance and scalability of multigate devices, thereby addressing the limitations of existing technologies.
Implementation Method 1
epitaxial growth to form the source/drain features
Implementation Method 2
a second etching process is performed that removes the patterned mask layer and portions of the semiconductor layer stack
Data Source
AI summary
Multi-gate devices and methods for fabricating such are disclosed herein. An exemplary method includes forming a semiconductor stack on a substrate, wherein the semiconductor stack includes a first semiconductor layers and a second semiconductor layers alternatively disposed, the first semiconductor layers and the second semiconductor layers being different in composition; patterning the semiconductor stack to form a semiconductor fin; forming a dielectric fin next to the semiconductor fin; forming a first gate stack on the semiconductor fin and the dielectric fin; etching to a portion of the semiconductor fin within a source/drain region, resulting in a source/drain recess; and epitaxially growing a source/drain feature in the source/drain recess, defining an airgap spanning between a sidewall of the source/drain feature and a sidewall of the dielectric fin.