Multi-Gate Source/Drain Profile to Suppress Mesa Leakage
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Solution Overview
Problem
Multi-gate devices, such as MBC transistors, experience current leakage issues due to the gate structure engaging the mesa structure under the channel members, leading to increased leakage current and reduced device performance.
Innovation Solution
A method is introduced to form source/drain features with a modified profile by recessing the source/drain regions and enlarging the openings to laterally extend into the mesa structure, using an undoped semiconductor layer at the bottom and doped layers above, which reduces leakage current by modifying the mesa structure's profile and replacing the dummy gate with a functional gate stack.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the gate structure engages the mesa structure directly, then gate control is improved, but leakage current increases
Solution Approach 1:
The patent introduces an intermediary structure (the modified mesa structure with recessed portions and modified sidewalls) between the gate structure and the substrate. This intermediary mesa structure allows the gate to maintain control over the channel while reducing direct engagement with the substrate, thereby suppressing leakage current paths without compromising gate control functionality.
Solution Approach 2:
The patent applies local quality modification by creating specific recessed portions in the mesa structure at locations where leakage current is most problematic. The mesa structure has different geometries in different regions - with recessed portions in certain areas and standard geometry in others - allowing localized suppression of leakage current while maintaining overall structural integrity and gate control.
2Object-generated harmful factors
If the mesa structure cross-sectional area is reduced, then leakage current is suppressed, but manufacturing complexity increases
Solution Approach 1:
The patent segments the mesa structure fabrication into distinct steps: forming the initial mesa structure, creating recessed portions in specific regions, and modifying sidewalls. This segmentation allows each step to be optimized independently and uses standard fabrication techniques (etching, deposition) to achieve the complex final structure, making the process more manageable and less complex than a monolithic approach.
Solution Approach 2:
The patent employs preliminary action by forming the basic mesa structure and its recessed portions before finalizing the gate structure and source/drain regions. This allows the mesa structure to be pre-configured with leakage-suppressing features, and subsequent processing steps can build upon this foundation without requiring complex integrated fabrication sequences.
3Object-generated harmful factors
If source/drain openings are enlarged laterally into the mesa structure, then leakage current is reduced, but manufacturing precision requirements increase
Solution Approach 1:
The patent utilizes parameter changes by modifying the geometry parameters of the source/drain openings - specifically enlarging them laterally into the mesa structure and creating modified profiles. By controlling parameters such as opening width, depth, and sidewall angles, the patent achieves effective leakage current reduction while using standard fabrication processes to manage precision requirements.
Data Source
AI summary
A semiconductor device and a method of forming the same are provided. In an embodiment, an exemplary semiconductor device includes a vertical stack of channel members disposed over a substrate, a gate structure wrapping around each channel member of the vertical stack of channel members, and a source/drain feature disposed over the substrate and coupled to the vertical stack of channel members, the source/drain feature comprising an undoped bottom layer and a doped upper layer, where a part of the undoped bottom layer of the source/drain feature is disposed directly under the gate structure.