Multigate Source/Drain Void Structure for GAA Gate Control
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Solution Overview
Problem
As gate-all-around (GAA) devices continue to scale, the addition of multiple stacked channel layers degrades their performance, posing challenges in maintaining gate control and mitigating short-channel effects while integrating with conventional IC manufacturing processes.
Innovation Solution
A method for fabricating a multigate device that includes forming a void in the source/drain region between the source/drain feature and the bottom surface, using a specific fabrication process that involves forming semiconductor layer stacks, recessing the source/drain regions, depositing a spacer layer, and etching to form inner spacers and a void, which enhances gate control and reduces leakage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If multiple stacked channel layers are added to GAA devices to improve gate control, then gate-channel coupling is enhanced, but device performance degrades due to increased complexity and manufacturing challenges
Solution Approach 1:
The source/drain region is segmented into multiple discrete features (first source/drain feature, second source/drain feature, third source/drain feature) stacked vertically, with voids between them. This segmentation allows independent control and optimization of each feature's interaction with the channel layers, improving gate control while managing complexity through modular structure
Solution Approach 2:
The patent transitions from conventional planar source/drain structures to a three-dimensional stacked configuration. Multiple source/drain features are arranged vertically at different heights, creating a multi-dimensional architecture that enhances gate-channel coupling by allowing the gate to wrap around and contact channel regions from multiple vertical levels
2Productivity
If GAA devices are scaled down to improve production efficiency and lower costs, then manufacturing productivity increases, but gate control and short-channel effect mitigation become more difficult
Solution Approach 1:
The gate structure is designed to extend around and wrap the channel region in a gate-all-around configuration, with source/drain features nested at different vertical levels. This nested arrangement allows the gate to maintain control over the channel from all directions, effectively mitigating short-channel effects even as device dimensions are scaled down
Solution Approach 2:
The fabrication process performs preliminary actions by forming voids between source/drain features before final gate formation. This preliminary structuring establishes the three-dimensional geometry early in the process, enabling subsequent gate materials to conformally coat the channel regions and ensuring optimal gate control is achieved before final device assembly
3Ease of manufacture
If conventional IC manufacturing processes are used to fabricate GAA devices, then ease of manufacture is maintained, but performance degradation occurs due to multiple stacked channel layers
Solution Approach 1:
The fabrication process employs self-aligned techniques where previously formed structures serve as alignment references for subsequent steps. For example, the first and second source/drain features serve as alignment guides for forming the third source/drain feature, and the gate structure automatically aligns to wrap the channel regions. This self-service approach maintains ease of manufacture while achieving the complex multi-layer geometry needed for high performance
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The proposed solution effectively improves the performance of GAA devices by maintaining gate control and reducing leakage, even as the devices scale, thereby addressing the challenges posed by multiple stacked channel layers.
Implementation Method 1
performing a deposition process to form an inner spacer layer in the source/drain recess. The inner spacer layer is disposed on the semiconductor layer stack and the mesa structure of the substrate
Implementation Method 2
the source/drain feature is grown from sidewalls of the second semiconductor layer
Data Source
AI summary
Semiconductor devices having improved source/drain features and methods for fabricating such are disclosed herein. An exemplary device includes a semiconductor layer stack disposed over a mesa structure of a substrate. The device further includes a metal gate disposed over the semiconductor layer stack and an inner spacer disposed on the mesa structure of the substrate. The device further includes a first epitaxial source/drain feature and a second epitaxial source/drain feature where the semiconductor layer stack is disposed between the first epitaxial source/drain feature and the second epitaxial source/drain feature. The device further includes a void disposed between the inner spacer and the first epitaxial source/drain feature.