Multi-Gate Inner Spacer Formation With Cyclic Nanowire-Safe Etching

Solution Overview

Problem

Current methods for forming inner spacers in gate-all-around (GAA) transistors face challenges in accurately controlling dimensions and positions, leading to variability in channel length and potential damage to nanowire channels during the etching process.

Innovation Solution

A cyclic process is introduced, alternating between a surface treatment process and a selective etching process, to precisely remove the inner spacer material layer from the channel region of GAA transistors, ensuring accurate control of spacer dimensions and maintaining the integrity of the nanowire channels.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If a conventional etching process is used to remove inner spacer material, then the etching speed is fast, but the critical dimension control precision deteriorates and nanowire damage occurs

Engineering Contradiction:

Improveetching speedVSAvoidcritical dimension control

Core Design Contradiction:

ProductivityVSManufacturing precision

Solution Approach 1:

The etching process is divided into multiple discrete etching steps separated by surface treatment steps. Each etching step removes a controlled portion of the inner spacer material, allowing for precise dimensional control while maintaining overall etching efficiency through the multi-step approach.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The patent implements a periodic cycle of surface treatment followed by etching. The surface treatment step prepares the nanowire surface between etching cycles, and the etching step removes material. This periodic alternation allows controlled material removal with precise dimensionality while preventing excessive etching that would damage the nanowires.

Inventive Principle:

Principle #19Periodic action

2Productivity

If a conventional etching process is used to remove inner spacer material, then the etching speed is fast, but nanowire integrity deteriorates due to excess etching

Engineering Contradiction:

Improveetching speedVSAvoidnanowire integrity

Core Design Contradiction:

ProductivityVSReliability

Solution Approach 1:

The etching process is divided into multiple discrete etching steps separated by surface treatment steps. Each etching step removes a controlled portion of the inner spacer material, allowing for precise dimensional control while maintaining overall etching efficiency through the multi-step approach.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The patent implements a periodic cycle of surface treatment followed by etching. The surface treatment step prepares the nanowire surface between etching cycles, and the etching step removes material. This periodic alternation allows controlled material removal with precise dimensionality while preventing excessive etching that would damage the nanowires.

Inventive Principle:

Principle #19Periodic action

3Device complexity

If a single etching step is used to remove inner spacer material, then the process complexity is low, but the channel length uniformity deteriorates

Engineering Contradiction:

Improveprocess complexityVSAvoidchannel length uniformity

Core Design Contradiction:

Device complexityVSManufacturing precision

Solution Approach 1:

The etching process is divided into multiple discrete etching steps separated by surface treatment steps. Each etching step removes a controlled portion of the inner spacer material, allowing for precise dimensional control while maintaining overall etching efficiency through the multi-step approach.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The surface treatment step acts as a feedback mechanism between etching steps, preparing the surface and allowing control adjustments. This feedback loop enables precise control of channel length uniformity by monitoring and adjusting the etching process parameters between steps.

Inventive Principle:

Principle #23Feedback

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

The cyclic process enhances the precision of critical dimension control, avoids excess etching that could damage the nanowires, and improves the uniformity of channel lengths across different layers, thereby maintaining the integrity and performance of the GAA transistors.

Implementation Method 1

selectively etching the surface portion of the dielectric material layer

Methodology Applied

Scientific EffectSelective etching:

Implementation Method 2

performing a treatment process to a surface portion of the dielectric material layer

Methodology Applied

Scientific EffectSurface treatment:

Data Source

PatentUS12336252B2Inner spacer formation in multi-gate transistors

Publication Date: 2025.06.17 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD

AI summary

A method for forming a semiconductor structure includes forming a fin on a semiconductor substrate. The fin includes channel layers and sacrificial layers stacked one on top of the other in an alternating fashion. The method also includes removing a portion of the fin to form a first opening and expose vertical sidewalls of the channel layers and the sacrificial layers, epitaxially growing a source/drain feature in the first opening from the exposed vertical sidewalls of the channel layers and the sacrificial layers, removing another portion of the fin to form a second opening to expose a vertical sidewall of the source/drain feature, depositing a dielectric layer in the second opening to cover the exposed vertical sidewall of the source/drain feature, and replacing the sacrificial layers with a metal gate structure in the second opening. The dielectric layer separates the source/drain feature from contacting the metal gate structure.