Multi-Gate Transistor STI Profile for Channel Height Tuning
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Solution Overview
Problem
The profile of the top surface of shallow trench isolation (STI) regions in multi-gate transistors affects the channel height, impacting current drive and leakage performance, and existing methods do not adequately address this issue.
Innovation Solution
The method involves forming shallow trench isolation regions with a controlled top surface profile by adjusting dopant concentration and etch rates in n-type and p-type regions, resulting in different channel heights for n-type and p-type transistors to optimize current drive and leakage performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If etch back and cleaning steps are performed during STI region formation, then the STI regions are successfully formed to separate adjacent transistors, but the top surfaces of the STI regions become recessed with center portions lower than edge portions, impacting multi-gate transistor performance
Solution Approach 1:
The patent applies preliminary action by forming a mandrel structure with a specific profile before depositing the dielectric material. The mandrel is formed with sidewalls that have different orientations (first sidewall with first orientation, second sidewall with second orientation), which pre-determines the final STI top surface profile. This preliminary structuring ensures that after etch back, the STI regions achieve the desired convex profile with center portions higher than edge portions, counteracting the recessing effect of etch back and cleaning steps.
Solution Approach 2:
The patent employs parameter changes by modifying the dielectric material deposition parameters to achieve selective height adjustment. Specifically, the dielectric material is deposited to a first height at center portions of the STI regions and a second height at edge portions, with the first height being greater than the second height. This differential deposition parameter change creates the convex top surface profile that compensates for subsequent etch back recessing and optimizes multi-gate transistor performance.
2Ease of manufacture
If uniform STI regions are formed, then manufacturing is simplified, but channel height cannot be optimized for both n-type and p-type transistors, limiting current drive and leakage performance
Solution Approach 1:
The patent applies local quality by creating STI regions with spatially varying properties. Specifically, center portions of the STI regions are formed with a first dielectric material having a first etch rate, while edge portions are formed with a second dielectric material having a second etch rate. This local differentiation allows the channel height to be optimized for both n-type and p-type transistors simultaneously, as the different etch rates enable selective height adjustment in different regions, improving both current drive and leakage performance without complicating the overall manufacturing process.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances current drive capability in n-type transistors and reduces leakage current in p-type transistors, improving overall device performance by fine-tuning the channel height through controlled dopant diffusion and etch back processes.
Implementation Method 1
performing an anneal process in driving dopants into the dielectric material layer, such that a dopant concentration in the dielectric material layer in the first region is higher than that in the second region
Data Source
AI summary
A semiconductor device includes a semiconductor substrate, first channel layers vertically stacked over a first fin-shaped base protruding from the semiconductor substrate, second channel layers vertically stacked over a second fin-shaped base protruding from the semiconductor substrate, an isolation feature extending from a sidewall of the first fin-shaped base to a sidewall of the second fin-shaped base, and a gate structure wrapping around each of the first and second channel layers. A top surface of the isolation feature intersects the sidewall of the first fin-shaped base at a first position and intersects the sidewall of the second fin-shaped base at a second position higher than the first position.