Multi-gate VDMOS Transistor Drive Current via Segmentation
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Solution Overview
Problem
Current VDMOS transistors have limited drive current due to a fixed number and width of conduction channels, restricting their performance in power electronics applications.
Innovation Solution
A multi-gate VDMOS transistor design is introduced, featuring multiple gate structures that increase the number of conduction channels, allowing for enhanced drive current by increasing the paths for current flow, along with optimized doped regions and metal layers for improved electrical connectivity and carrier mobility.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If a conventional single-gate VDMOS structure is used, then the device structure is simple and easy to manufacture, but the drive current is limited due to a fixed number of conduction channels
Solution Approach 1:
The gate structure is segmented into multiple gates (first gate and second gate) that are spatially separated and independently configured. Each gate controls its own conduction channel, allowing the drive current to be increased by providing multiple parallel conduction paths rather than relying on a single gate structure.
Solution Approach 2:
The invention transitions from a single-gate planar structure to a multi-gate three-dimensional structure where gates are positioned at different locations and orientations. This dimensional expansion allows multiple conduction channels to form simultaneously, increasing the overall drive current capability without simply scaling up the single gate size.
2Productivity
If the number of conduction channels is increased to enhance drive current, then the drive current improves, but the device structure becomes more complex
Solution Approach 1:
The conduction channels are segmented into multiple independent paths, each controlled by its own gate. The first conduction channel is controlled by the first gate and the second conduction channel is controlled by the second gate, allowing current to flow through multiple parallel channels simultaneously, thereby increasing drive current while maintaining structured organization.
Solution Approach 2:
Multiple conduction channels are merged into a single device structure where they operate in parallel. The first doped region, second doped region, and associated channels are combined within the same semiconductor substrate, allowing the benefits of multiple channels to be realized without requiring separate devices.
3Productivity
If multiple doped regions are introduced to form additional conduction channels, then carrier mobility and drive current improve, but the manufacturing process becomes more complex
Solution Approach 1:
The doped regions are formed as preliminary structures before final device operation. The first doped region and second doped region are pre-configured in the semiconductor substrate during fabrication, establishing the conduction channels in advance. This preliminary doping action simplifies subsequent processing steps and ensures proper carrier mobility from the outset.
Solution Approach 2:
Different doped regions are introduced with specific local properties optimized for their respective functions. The first doped region has doping characteristics optimized for the first conduction channel, while the second doped region has characteristics optimized for the second conduction channel, allowing each region to contribute maximally to carrier mobility in its local area.
Data Source
AI summary
Various embodiments provide multi-gate VDMOS transistors. The transistor can include a substrate having a first surface and a second surface opposite to the first surface, a drift layer on the first surface of the substrate, and an epitaxial layer on the drift layer. The transistor can further include a plurality of trenches. Each trench can pass through the epitaxial layer and a thickness portion of the drift layer. The transistor can further include a plurality of gate structures. Each gate structure can fill the each trench. The transistor can further include a plurality of doped regions in the epitaxial layer. Each doped region can surround a sidewall of the each gate structure. The transistor can further include a source metal layer on the epitaxial layer to electrically connecting the plurality of doped regions, and a drain metal layer on the second surface of the substrate.