Stacked Multi-Gate Transistor Wiring Layout for Dense 3D Integration
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Solution Overview
Problem
Existing semiconductor devices face challenges in achieving high integration density and improved performance due to limitations in scaling and current control capabilities, particularly with short channel effects.
Innovation Solution
A semiconductor device design featuring a stacked multi-gate transistor with specific structural elements such as active patterns, gate structures, cutting structures, and through-vias that enhance electrical connectivity and integration density.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If conventional planar transistors are used, then manufacturing is simpler, but integration density and current control capability are limited
Solution Approach 1:
The patent transitions from conventional planar (2D) transistor structures to three-dimensional multi-gate transistor structures with stacked active patterns extending in the vertical direction. This dimensional change enables higher integration density by utilizing the third dimension for device stacking while maintaining effective gate control through the multi-gate configuration that wraps around the channel region.
Solution Approach 2:
The transistor structure is segmented into multiple active patterns (first lower active pattern, first upper active pattern, second lower active pattern, second upper active pattern) stacked vertically. Each active pattern is controlled by its own gate structure, allowing independent optimization of current control and density while maintaining manufacturing feasibility through modular construction.
2Reliability
If gate length is increased to improve current control, then current control capability improves, but device area increases
Solution Approach 1:
Instead of increasing gate length in the planar direction, the patent employs multi-gate structures that wrap around the vertical channel region. The gates extend along the vertical direction and surround the active patterns from multiple sides, providing enhanced electrostatic control without increasing the lateral footprint of the device.
Solution Approach 2:
The gate structures are positioned to surround and control the active patterns from multiple directions. The first gate structure controls the first active pattern while the second gate structure controls the second active pattern, with both gates nested in the vertical stacking arrangement to maximize control efficiency within minimal area.
3Productivity
If conventional transistor scaling is applied, then integration density increases, but short channel effects worsen
Solution Approach 1:
The patent uses vertically stacked active patterns with gates that control the channel from multiple directions including the vertical dimension. This three-dimensional gate control provides superior electrostatic management that suppresses short channel effects even as devices are scaled to smaller dimensions and higher densities.
Solution Approach 2:
The transistor structure employs composite material arrangements with alternating semiconductor active patterns and insulating materials in the vertical stack. This composite structure enables precise control of electrical properties while maintaining physical stability and suppressing short channel effects through the multi-material interface design.
Data Source
AI summary
A semiconductor device including a stacked multi-gate transistor includes a substrate, a first active pattern including a first lower active pattern and a first upper active pattern, a second active pattern including a second lower active pattern and a second upper active pattern, a first gate structure, a second gate structure on the second active pattern, the first gate structure and the second gate structure are aligned, a cutting structure between the first active pattern and the second active pattern, the cutting structure separating the first gate structure and the second gate structure, a front wiring pattern that extends on an upper surface of the cutting structure, a first back wiring pattern, and a first through-via that extends into the substrate and the cutting structure, the first through-via electrically connects the front wiring pattern and the first back wiring pattern.