Multilayer Capacitor Electrode Stacking for ESR and ESL Reduction
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Solution Overview
Problem
Multilayer capacitors face challenges in achieving high capacitance while minimizing equivalent series resistance (ESR) and equivalent serial inductance (ESL) to support efficient power delivery in compact electronic devices.
Innovation Solution
A multilayer capacitor design featuring a capacitor body with alternating dielectric layers and internal electrodes, where specific electrode configurations and connection portions enhance capacitance and reduce ESR and ESL by optimizing electrode placement and overlap, allowing for efficient charge accumulation and reduced inductance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If the thickness of electronic components is reduced to meet smartphone design requirements, then the weight and thickness of devices are reduced, but the integration density and capacitance of passive elements must be increased to maintain functionality
Solution Approach 1:
The patent transitions from planar electrode arrangements to a three-dimensional stacked configuration with alternating dielectric layers and internal electrodes. This vertical stacking in the thickness direction enables increased capacitance within a reduced footprint area, effectively solving the contradiction between reduced device thickness and maintained integration density.
Solution Approach 2:
Multiple dielectric layers and internal electrodes are nested within each other in a compact stacked structure. The alternating layers of dielectric material and conductive electrodes are embedded one within another, maximizing the use of available space and achieving high integration density while maintaining thin overall dimensions.
2Quantity of substance
If more multilayer capacitors are mounted on a circuit to increase capacitance, then the total capacitance increases, but the connection length and equivalent series inductance (ESL) increase
Solution Approach 1:
The patent moves from horizontal expansion (mounting more capacitors on the circuit plane) to vertical integration (stacking multiple dielectric and electrode layers within a single capacitor body). This dimensional shift reduces the number of discrete components needed and shortens connection paths, thereby reducing ESL while achieving the required capacitance.
Solution Approach 2:
Multiple capacitor elements are merged into a single integrated multilayer structure where alternating dielectric and electrode layers form multiple capacitive units within one component. This consolidation reduces the total connection length and number of external connections required, lowering equivalent series inductance.
3Use of energy by moving object
If multilayer capacitors are designed with increased capacitance and reduced connection length, then power efficiency improves, but the structural complexity of alternating dielectric and electrode layers increases
Solution Approach 1:
The capacitor is segmented into multiple repeating units of dielectric layers and internal electrodes stacked in sequence. This modular segmentation allows for systematic construction of high-capacitance structures while maintaining manufacturing feasibility through repetitive layering processes.
Solution Approach 2:
The patent employs composite structures combining different dielectric materials and conductive electrode materials in alternating layers. This composite approach enables optimization of electrical properties (capacitance, ESR, ESL) while managing structural complexity through material selection and layer configuration.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The design achieves increased capacitance and reduced ESR and ESL, improving power efficiency and integration density, suitable for applications in smartphones and other electronic devices.
Implementation Method 1
a capacitor body including first and second surfaces opposing each other, third and fourth surfaces connected to the first and second surfaces and opposing each other, fifth and sixth surfaces connected to the first and second surfaces and to the third and fourth surfaces and opposing each other, and including first and second dielectric layers, a plurality of first internal electrodes and a plurality of second internal electrodes alternately layered
Implementation Method 2
The design achieves increased capacitance and reduced ESR and ESL, improving power efficiency and integration density
Implementation Method 3
to have low equivalent serial inductance (ESL) to significantly reduce a ripple of a power current
Data Source
AI summary
Provided is a multilayer capacitor and a board on which the multilayer capacitor is mounted. The multilayer capacitor includes a capacitor body including first to six surfaces, first and second dielectric layers, and first and second internal electrodes; first and second external electrodes disposed on the first surface of the capacitor body; the first and second dielectric layers are alternately layered in a first direction such that the first internal electrode of the first dielectric layer overlaps the second internal electrode of the second dielectric layer in the first direction, and the second internal electrode of the first dielectric layer overlaps the first internal electrode of the second dielectric layer in the first direction.