5-Terminal Multilayer Capacitor Layout for Low ESL in Small Footprints
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Solution Overview
Problem
The increasing demand for miniaturization and high capacitance in multilayer ceramic capacitors, particularly in smartphones, is hindered by the need to reduce source impedance and mounting space, which is challenging due to limitations in reducing the current loop and chip size in conventional MLCCs.
Innovation Solution
A 5-terminal multilayer electronic component design with alternately stacked internal electrode layers and external electrodes, optimized to minimize the current loop and chip size, while maintaining low equivalent series inductance (ESL) and allowing for diverse capacitance levels by varying the overlap areas of internal electrodes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the number of internal electrodes is increased to reduce source impedance, then the equivalent series inductance (ESL) is reduced, but the mounting space occupied by the component increases
Solution Approach 1:
The internal electrode structure is segmented into multiple electrodes (first to fourth internal electrodes) arranged in an alternating pattern with dielectric layers. This segmentation allows the current path to be divided into multiple parallel paths, reducing the equivalent series inductance while maintaining a compact footprint that minimizes mounting space.
2Area of stationary object
If the chip size is reduced to minimize mounting space, then the mounting area is decreased, but the current loop area cannot be sufficiently reduced to achieve low ESL
Solution Approach 1:
The patent transitions from a planar current loop configuration to a three-dimensional stacked configuration with alternating internal electrodes and dielectric layers. This dimensional change allows the current path to fold back on itself within the vertical dimension, significantly reducing the horizontal current loop area and thus the ESL, while maintaining a compact chip footprint for minimal mounting space.
3Device complexity
If conventional two-terminal capacitor configuration is used, then the structure is simple, but the mounting space and source impedance performance are insufficient for high-performance applications
Solution Approach 1:
Multiple capacitor units with alternating internal electrodes are merged into a single integrated component body. The first to fourth internal electrodes are alternately disposed with dielectric layers, creating multiple capacitance elements that function together as one component. This merging achieves low source impedance and reduced ESL while maintaining a compact single-component structure suitable for dense mounting.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design effectively reduces ESL, minimizes mounting space, and simplifies the mounting process by integrating the functionality of four two-terminal capacitors into a single component, enhancing the performance and compactness of electronic devices.
Implementation Method 1
a connection electrode penetrating through the first and second internal electrode layers, spaced apart from the first to fourth internal electrodes, and connected to the fifth internal electrode
Implementation Method 2
a body including a capacitance forming portion in which the first internal electrode layer and the second internal electrode layer are alternately disposed
Implementation Method 3
a first internal electrode layer including a first dielectric layer and first to fourth internal electrodes disposed to be spaced apart from each other on the first dielectric layer
Data Source
AI summary
A multilayer electronic component may include a first internal electrode layer including a first dielectric layer and first to fourth internal electrodes disposed to be spaced apart from each other on the first dielectric layer, a second internal electrode layer including a second dielectric layer and a fifth internal electrode disposed on the second dielectric layer, a body including a capacitance forming portion in which the first internal electrode layer and the second internal electrode layer are alternately disposed, a connection electrode penetrating through the first and second internal electrode layers, spaced apart from the first to fourth internal electrodes, and connected to the fifth internal electrode, first to fourth external electrodes disposed to be connected to the first to fourth internal electrodes, respectively, on the body, and a fifth external electrode disposed to be connected to the connection electrode on the body.