Multilayer Coupling Capacitor Layout for Low-Loss PCB Signals
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Solution Overview
Problem
Existing multilayer coupling capacitors face challenges in meeting the performance criteria for high-speed environments, particularly in miniaturized and denser circuit boards, with a need for improved operational characteristics and a smaller footprint.
Innovation Solution
A surface mount multilayer coupling capacitor is designed with alternating dielectric and internal electrode layers in a single, unitary package, featuring external terminals on both surfaces and optimized internal electrode layer arrangements to reduce electrical length and minimize insertion loss.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If traditional multilayer coupling capacitors are used with conventional electrode layer configurations, then manufacturing is simplified, but insertion loss exceeds 0.25 dB in high-speed environments
Solution Approach 1:
The patent applies local quality by making the internal electrode layers non-uniform in width, with the first internal electrode layer having a different width than the second internal electrode layer. This localized variation in electrode geometry optimizes the electrical characteristics and reduces insertion loss specifically in the high-frequency signal path, rather than using a uniform configuration throughout the capacitor structure.
Solution Approach 2:
The patent changes the geometric parameters of the internal electrode layers, specifically varying the width of different electrode layers to optimize performance. By adjusting the width parameters of the first and second internal electrode layers differently, the capacitor achieves reduced insertion loss (0.25 dB or less) while maintaining the multilayer structure for manufacturing feasibility.
2Area of stationary object
If capacitor size is reduced for miniaturized circuit boards, then footprint is smaller, but maintaining low insertion loss becomes more difficult
Solution Approach 1:
The patent transitions from a conventional single-layer electrode configuration to a multilayer electrode structure with alternating dielectric and electrode layers. By utilizing the vertical dimension (stacking multiple layers) rather than only expanding in the horizontal plane, the capacitor achieves low insertion loss performance within a compact footprint suitable for miniaturized circuit boards.
Solution Approach 2:
The patent employs a composite structure with alternating dielectric layers and internal electrode layers, where each layer is made of different materials with optimized properties. This composite multilayer construction enables the capacitor to maintain low insertion loss while occupying minimal board space, as the different materials contribute different functional properties to the overall structure.
3Speed
If external terminals are formed only on one surface, then manufacturing is simpler, but electrical length increases reducing high-frequency performance
Solution Approach 1:
The patent segments the terminal formation across two different surfaces of the capacitor body, with external terminals formed on both the first surface and the second surface. This segmentation allows the electrical path to be shortened by providing direct access points on opposite faces, improving high-frequency signal transmission without requiring excessively complex manufacturing processes.
Data Source
Figure 1A~1C
Figure 2~3
AI summary
The present invention is directed to a surface mount coupling capacitor and a circuit board containing a surface mount coupling capacitor. The coupling capacitor includes a main body containing at least two sets of alternating dielectric layers and internal electrode layers. The coupling capacitor includes external terminals electrically connected to the internal electrode layers wherein the external terminals are formed on a top surface of the coupling capacitor and a bottom surface of the coupling capacitor opposing the top surface of the coupling capacitor.