Multilayer Capacitor Margin Porosity for Sintering Reliability
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Solution Overview
Problem
Multilayer ceramic capacitors face reliability issues due to differences in reduction rates between the core, margin, and cover portions, leading to deformations and product defects like cracks or breakage, as a result of non-uniform stress during sintering.
Innovation Solution
A multilayer electronic component design that includes a body with alternately disposed internal electrodes and dielectric layers, a cover portion with a second dielectric layer, and a margin portion with a dielectric pattern having higher porosity than the first dielectric layer, which helps in reducing the difference in reduction rates and preventing deformation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If the dielectric layer and internal electrode are configured with reduced thickness to achieve miniaturization and high capacity, then the size is reduced and capacity is increased, but a mismatch occurs between elements due to difference in reduction rates during sintering, deteriorating reliability
Solution Approach 1:
The patent applies local quality by configuring the dielectric layer with different properties in different regions: the first dielectric layer in the core portion has different characteristics than the second dielectric layer in the margin portion. Specifically, the dielectric layers have different reduction rates during sintering, with the margin portion dielectric layer having a higher reduction rate to compensate for differential shrinkage stress. This local differentiation resolves the contradiction by allowing miniaturization while maintaining reliability through region-specific material properties.
2Device complexity
If only a dielectric sheet is present in the margin or cover portion where the internal electrode is not disposed, then the structure is simplified, but a difference occurs in reduction or expansion during burn-out and sintering, causing deformations such as distortion
Solution Approach 1:
The patent implements local quality by making the margin portion dielectric layer (second dielectric layer) have different properties from the core portion dielectric layer (first dielectric layer). The second dielectric layer is configured with a higher reduction rate during sintering to match and compensate for the shrinkage of adjacent internal electrodes. This prevents differential stress and eliminates deformations like distortion, while maintaining a relatively simple overall structure without requiring complex additional components.
3Ease of manufacture
If the reduction rate difference between core and margin portions is not controlled, then manufacturing is easier, but non-uniform stress during sintering leads to cracks or breakage due to reverse connection
Solution Approach 1:
The patent applies parameter changes by controlling the reduction rate parameter of the dielectric layers. The second dielectric layer in the margin portion is specifically designed to have a higher reduction rate than the first dielectric layer in the core portion. This parameter adjustment ensures uniform dimensional changes during sintering, preventing non-uniform stress that would cause cracks or breakage, while maintaining ease of manufacture through a straightforward lamination and sintering process.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The design enhances the reliability of the multilayer ceramic capacitor by minimizing the deviation in reduction rates between the active and cover portions, thereby preventing cracks and breakage, and ensuring consistent performance.
Implementation Method 1
a margin portion covering a side surface of the one of the internal electrodes other than a side surface connected to the external electrode and including a dielectric pattern having a porosity higher than that of one of the plurality of first dielectric layers
Implementation Method 2
a difference in reduction rates in sintering
Data Source
AI summary
A multilayer electronic component includes a body including a plurality of first dielectric layers, an active portion in which internal electrodes are alternately disposed, and a cover portion disposed the active portion in a first direction of the body, a direction in which the plurality of first dielectric layers are laminated, and including a second dielectric layer; and an external electrode disposed externally on the body and connected to one of the internal electrodes. The body includes a margin portion covering a side surface of the one of the internal electrodes other than a side surface connected to the external electrode and including a dielectric pattern having a porosity higher than that of one of the plurality of first dielectric layers.