Multilayer Chip Capacitor with Alternating Laminated Units for PDN Impedance
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Solution Overview
Problem
The increasing complexity of power distribution networks (PDN) in microprocessor units (MPUs) due to higher speeds and integration levels results in a decrease in target impedance, requiring a broader frequency range coverage with a larger number of decoupling capacitors, which is inefficient and space-consuming.
Innovation Solution
A multilayer chip capacitor design featuring alternating laminated portions with different capacitance units and a capacitance adjusting portion, allowing for reduced equivalent series inductance (ESL) and increased capacitance, enabling a single capacitor to cover a broad frequency range from hundreds of kHz to hundreds of MHz with fewer components.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If multiple decoupling capacitors are used to cover broad frequency range, then impedance reduction effectiveness is improved, but device complexity and mounting space increase
Solution Approach 1:
The patent combines multiple capacitor units with different capacitance values (first capacitor unit with first capacitance, second capacitor unit with second capacitance) into a single multilayer chip capacitor structure. This merging allows the single capacitor to provide impedance reduction across a broad frequency range that would otherwise require multiple separate capacitors, thereby reducing device complexity and mounting space while maintaining impedance reduction effectiveness
Solution Approach 2:
The multilayer chip capacitor is designed to perform multiple functions within a single component: it provides decoupling capacitance for different frequency ranges simultaneously through its multiple capacitor units, and also provides low equivalent series inductance (ESL) performance through its specific electrode configuration. This multi-functionality eliminates the need for multiple specialized capacitors
2Reliability
If multiple decoupling capacitors are used to cover broad frequency range, then impedance reduction effectiveness is improved, but mounting space increases
Solution Approach 1:
The patent merges multiple capacitor functions into a single physical component, replacing what would traditionally require multiple discrete capacitors occupying separate mounting spaces. The integrated structure with multiple capacitor units in one package dramatically reduces the total area required on the circuit board while maintaining the ability to reduce impedance across broad frequency ranges
3Ease of manufacture
If conventional MLCC structure is used, then manufacturing simplicity is maintained, but frequency range coverage is limited
Solution Approach 1:
The patent segments the capacitor structure into multiple distinct capacitor units (first capacitor unit, second capacitor unit) with different capacitance values, each contributing to different frequency range coverage. This segmentation is achieved through alternating polarities of inner electrodes and specific lamination patterns, allowing broad frequency coverage while maintaining compatibility with conventional MLCC manufacturing processes
Solution Approach 2:
The patent extends the functional capabilities of the capacitor by utilizing the vertical lamination dimension to create multiple capacitor units with different capacitances. By varying the number of laminated layers and their arrangement in the vertical direction, the capacitor achieves broad frequency range coverage without complicating the horizontal manufacturing process
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design effectively reduces PDN impedance to a target level across a wide frequency range using fewer capacitors, simplifying the design and reducing the number of decoupling capacitors needed, thereby improving efficiency and mounting density.
Implementation Method 1
a capacitor body having a plurality of dielectric layers laminated therein, the capacitor body including first and second capacitor units having capacitances different from each other; and first to fourth outer electrodes formed on an outer surface of the capacitor body
Data Source
AI summary
There is provided a multilayer chip capacitor including: a capacitor body including first and second capacitor units; and first to fourth outer electrodes, wherein the first capacitor unit includes at least one pair of first and second inner electrodes, the second capacitor unit includes at least one pair of third and fourth inner electrodes, an alternate laminated portion is formed in one area within the capacitor body, the alternate laminated portion having the first to fourth inner electrodes sequentially laminated therein, and a capacitance adjusting portion is formed in another area within the capacitor body, the capacitance adjusting portion having at least one of the one pair of first and second inner electrodes and the one pair of third and fourth inner electrodes laminated repeatedly.