Multilayer Circuit Board Warpage Reduction via Segmented Dual-Stack Design
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Solution Overview
Problem
The increasing number of layers in multilayer circuit structures leads to severe warpage issues, affecting the yield rate of both circuit boards and package structures, particularly when applied to complex electronic product designs.
Innovation Solution
The formation of multilayer structures on both surfaces of an interconnect substrate, with the topmost layer pattern engaging with the conductive structure pattern, reduces the number of layers and enhances bonding reliability, thereby addressing warpage and yield rate concerns.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If the number of layers in multilayer circuit structure is increased to satisfy complex electronic product design, then the circuit density and internal layout space are improved, but the warpage issue becomes severe
Solution Approach 1:
The patent divides the multilayer circuit structure into two separate multilayer structures, each with fewer layers, bonded to opposite sides of a core substrate. This segmentation reduces the layer count per structure, thereby minimizing warpage while maintaining the required circuit density through distributed routing across both structures.
Solution Approach 2:
The patent transitions from a single-stack multilayer structure to a dual-stack configuration bonded to opposite sides of the core substrate. This dimensional change allows circuit routing to occur in two separate planes, reducing the vertical layer count per structure and consequently reducing warpage while preserving overall circuit capacity.
2Volume of stationary object
If the number of layers in multilayer circuit structure is increased, then the internal layout space is increased, but the yield rate of package structure is affected
Solution Approach 1:
By segmenting the high-layer-count structure into two lower-layer structures bonded to opposite sides of the core substrate, the patent reduces manufacturing complexity and warpage risks, thereby improving yield rate while maintaining adequate internal layout space through distributed circuit arrangement.
3Adaptability or versatility
If the multilayer structure is applied to package structure, then the functionality is enhanced, but the warpage issue occurs in package structure
Solution Approach 1:
The patent applies segmentation by creating two separate multilayer structures with reduced layer counts bonded to opposite sides of the core substrate. This reduces warpage in the package structure while maintaining enhanced functionality through the combined capabilities of both multilayer structures.
Solution Approach 2:
The patent employs asymmetric bonding where multilayer structures are attached to opposite sides of the core substrate, creating a balanced configuration that compensates for thermal and mechanical stresses, thereby reducing warpage while preserving functional versatility.
Data Source
AI summary
A circuit board including an interconnect substrate and a multilayer structure is provided. The interconnect substrate includes a core layer and a conductive structure disposed on the core layer. The multilayer structure is disposed on the conductive structure. The multilayer structure includes a plurality of dielectric layers and a plurality of circuit structures. The circuit structures are disposed in the dielectric layers. A topmost layer in the circuit structures is exposed to the dielectric layers to be in contact with the conductive structure. A pattern of the topmost layer in the circuit structures and a pattern of a top surface of the conductive structure are engaged with each other.