Multilayer Conductive Circuit for Chip Packaging
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Solution Overview
Problem
Typical power semiconductor devices have limited load current due to thin metal structures and voltage differences that cause synchronization issues in circuit transmission.
Innovation Solution
A semiconductor device design featuring a substrate with alternating extension parts on conduction layers, increasing the cross-sectional area of the metal structure through attach materials like solder bumps or copper pillars, and an isolation layer made of nitride and oxide materials to enhance load current and reduce voltage differences.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If the metal structures in the chip are made thinner to reduce size, then the device footprint is reduced, but the load current capacity is limited
Solution Approach 1:
The patent transitions from two-dimensional planar metal structures to three-dimensional multilayer stacked metal structures. Multiple metal layers are stacked vertically with alternating polarity, creating a vertical current path that increases effective cross-sectional area without increasing chip footprint. This dimensional transition resolves the contradiction by providing higher current capacity through the third dimension.
Solution Approach 2:
The patent employs composite metal structures consisting of multiple metal layers with different materials and properties. The alternating polarity layers are connected through vias and conductive structures, creating a composite conductive system that achieves higher effective cross-sectional area and current capacity while maintaining compact chip dimensions.
2Device complexity
If the metal structures are made thinner, then the device complexity is reduced, but the voltage difference increases causing synchronization issues
Solution Approach 1:
The patent designs alternating polarity metal layers that are substantially equipotential within each layer, reducing voltage differences across the chip. By maintaining equal potential distribution in each metal layer and providing multiple parallel current paths through the stacked structure, voltage synchronization is improved and timing issues are reduced.
Solution Approach 2:
The patent segments the current path into multiple discrete metal layers connected through vias. This segmentation creates multiple parallel current paths that distribute current flow and reduce voltage drops. The segmented structure allows better control of voltage distribution and reduces synchronization issues while maintaining manageable complexity through modular layer design.
Data Source
AI summary
A semiconductor device includes a substrate and a chip. The substrate has a first conduction layer, a second conduction layer, and an isolation layer disposed between the first conduction layer and the second conduction layer. The first conductive layer has a first portion and a second portion spaced apart from the first portion, and each of the first portion and the second portion includes a main part and a plurality of extension parts extending from the main part. The chip is disposed on the extension parts of the first portion and the second portion of the first conductive layer.