Multilayer Display Wiring Layout for High-Pixel-Density Panels
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Solution Overview
Problem
The increasing number of pixels in display devices, such as head-mounted displays, leads to an increase in signal lines, which in turn increases the device size and area, posing a challenge in efficiently arranging these signal lines.
Innovation Solution
A display device design that includes transistors with different semiconductor materials and gate electrodes in separate layers, along with specific wiring arrangements that overlap and are positioned at distances, optimizing the layout to minimize space usage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If the number of pixels is increased to achieve high-definition display, then the image quality is improved, but the number of signal lines increases and the device area increases
Solution Approach 1:
The patent applies three-dimensional stacking of transistor layers to reduce the planar area occupied by signal lines. By arranging transistors in multiple layers (first layer with first transistors, second layer with second transistors) vertically above the substrate, the design transitions from a two-dimensional layout to a three-dimensional structure, allowing more pixels and signal lines to be packed into a smaller footprint area.
Solution Approach 2:
The patent implements nesting by placing the second layer of transistors above and overlapping with the first layer of transistors. The second gate electrode is positioned above the first gate electrode, and various wirings are arranged in overlapping configurations across different layers, creating a nested vertical structure that maximizes space utilization and reduces the overall device area.
2Quantity of substance
If the number of signal lines is increased to support more pixels, then the pixel density is improved, but the wiring area and device complexity increase
Solution Approach 1:
The patent segments the transistor structure into two distinct layers: first transistors in the first layer and second transistors in the second layer. This segmentation allows signal lines to be distributed across different layers, reducing the complexity of wiring in any single layer and making the overall wiring structure more manageable despite the increased number of signal lines required for high pixel density.
Solution Approach 2:
By utilizing the vertical dimension with multiple transistor layers, the patent provides additional routing paths for signal lines. Signal lines can be distributed across different layers and connected through vertical interconnections, which reduces the complexity of planar wiring arrangements and allows for more efficient organization of the increased number of signal lines needed for high pixel density.
Data Source
AI summary
A display device includes a first transistor including a first material as a semiconductor material and including a first gate electrode, a second transistor including a second material as a semiconductor material different from the first material and including a second gate electrode arranged in a different layer from the first gate electrode, a first wiring arranged in the same layer as the first gate electrode, a second wiring arranged in the same layer as the second gate electrode, and a third wiring formed in the same layer as a source electrode or a drain electrode of the second transistor and different from the first wiring and the second wiring. The first wiring, the second wiring and the third wiring overlap in a plan view.