Multilayer Flexible Planar Embedded Laminated Electrode
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Solution Overview
Problem
Current methods for manufacturing organic single crystal field effect transistors face challenges such as thermal radiation damage to organic semiconductors and limited device integration, particularly due to protruding electrodes that lead to non-uniform conduction channels and reduced performance.
Innovation Solution
A multilayer flexible planar embedded laminated electrode structure is developed, where the electrodes and insulating layer are in the same plane, allowing complete contact with organic semiconductors, and can be reused, suitable for various crystal sizes, using a method involving octadecyl trichloro silane modification, photoetching, and polydimethylsiloxane coating, enabling high-precision and complex pattern manufacturing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If conventional vacuum deposition mask method is used to directly construct electrodes on organic semiconductor, then device integration is improved, but thermal radiation damage to organic semiconductor occurs causing loss of field effect performance
Solution Approach 1:
The patent introduces a sacrificial layer (e.g., photoresist) as an intermediary between the electrode and organic semiconductor. This sacrificial layer is deposited first, then electrodes are formed on top of it through vacuum deposition. After electrode formation, the sacrificial layer is removed via photoetching, leaving clean electrodes on the semiconductor without direct thermal exposure during deposition. This mediator enables high integration while protecting the organic material from thermal damage.
2Object-affected harmful factors
If gold film stamp or nanobelt electrode methods are used to manufacture organic field effect transistor, then thermal radiation damage is avoided by operating at room temperature, but probe station operation is required which requires fine operation and is suitable for manufacturing a single device only, thus device integration is limited
Solution Approach 1:
The patent replaces the manual probe station mechanical system with an automated vacuum deposition and photoetching system. Instead of manually positioning and stamping electrodes using probe stations, the invention uses automated vacuum deposition to deposit electrodes across multiple devices simultaneously, followed by automated photoetching processes. This substitution enables batch manufacturing of multiple devices while maintaining room temperature operation to protect the organic semiconductor.
Solution Approach 2:
The patent performs preliminary actions by first depositing the sacrificial layer across the entire substrate before forming electrodes. This preliminary sacrificial layer deposition enables subsequent batch electrode formation and pattern definition through photoetching, allowing multiple devices to be manufactured simultaneously rather than one-by-one as required by probe station methods.
3Productivity
If bottom-gate bottom-contact configuration is used with electrostatic adsorption method, then device integration is improved and multiple devices can be manufactured at one time, but source/drain/gate electrodes and insulating layer are separated from semiconductor which requires fine operation and limits crystal size usage
Solution Approach 1:
The patent merges the electrode and insulating layer formation into a single integrated process by using the sacrificial layer as a common foundation. Both the electrodes and the insulating layer are formed on top of the same sacrificial layer, which is then removed together. This merging eliminates the need for separate fine operation steps to position electrodes and insulators independently, simplifying the manufacturing process while maintaining high device integration.
4Adaptability or versatility
If protruding electrode structure is used where source/drain electrodes are projected from insulating layer surface, then larger size crystal and wider channel length are accommodated, but organic semiconductor cannot be completely fit with insulating layer leading to air gap formation near electrodes which affects device performance
Solution Approach 1:
The patent transitions from a protruding 3D electrode structure to a planar 2D embedded electrode structure. By forming electrodes and insulating layer at the same plane level through the sacrificial layer method, the semiconductor can make complete contact with both structures without air gaps. This dimensional change from protruding to planar configuration eliminates the fit problem while still accommodating various crystal sizes through flexible pattern design.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach allows for high-performance organic single crystal field effect transistors to be manufactured at room temperature, avoiding radiation damage, with improved integration and flexibility, enabling the production of devices with various sizes and complex patterns, and achieving higher mobility compared to existing technologies.
Implementation Method 1
a octadecyl trichloro silane is connected on the surface of a substrate
Implementation Method 2
connecting mercaptopropyl trimethoxysilane at surfaces of metal electrodes of the source electrode, the drain electrode and the gate electrode using a vapor phase method
Implementation Method 3
a polydimethylsiloxane is spin-coated respectively on the surfaces of the source electrode, the drain electrode and the gate electrode obtained in step (2) and cured
Implementation Method 4
oxygen plasma treatments are performed on the surface of metal electrode of the gate electrode and polydimethylsiloxane surfaces of the source electrode and the drain electrode respectively, i.e., hydroxy being formed on the surfaces
Implementation Method 5
the gate electrode, the source electrode and the drain electrode are connected to form an integral, i.e., the multilayer flexible planar embedded laminated electrode being obtained
Data Source
AI summary
A flexible planar embedded laminated electrode can be manufactured by a method in which an octadecyl trichloro silane connected on the surface of a substrate; a source electrode, a drain electrode and a gate electrode are manufactured using photoetching; mercaptopropyl trimethoxysilane is connected at surfaces of metal electrodes of the source electrode, the drain electrode and the gate electrode; a polydimethylsiloxane is spin-coated on the respective surfaces for metal electrodes of the above electrodes; the gate electrode spin-coated with polydimethylsiloxane is removed from the substrate; oxygen plasma treatments are performed, so as to form hydroxy on the surfaces; the source electrode and the drain electrode are cut, and the gate electrode, the source electrode and the drain electrode are connected to form an integral to obtain the flexible planar embedded laminated electrode.