Multilayer Interdigitated Capacitor Structure for High Density
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Solution Overview
Problem
The capacitance density of traditional parallel plate capacitor structures in deep sub-micron complementary metal-oxide semiconductor (CMOS) is low due to limited minimum distance between electrodes, and interdigitated capacitor structures face limitations in crossover capacitance, necessitating an improvement in capacitor design to enhance capacitance, particularly in deep sub-micron CMOS technology.
Innovation Solution
A capacitor structure featuring multiple conductive line levels with vias arranged alternately between neighboring levels on separate co-planes, allowing for staggered or arrayed projections without overlap, which increases capacitance and reduces pattern transferring deviation and time-dependent dielectric breakdown issues.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If traditional parallel plate capacitor structure is used, then manufacturing is simple, but capacitance density is low due to limited minimum distance between electrodes
Solution Approach 1:
The patent transitions from a traditional two-dimensional parallel plate structure to a three-dimensional interdigitated multilayer structure. Multiple conductive line levels are stacked vertically with vias connecting alternating levels, creating an interdigitated pattern that utilizes the third dimension (height) to increase effective electrode surface area and capacitance density without increasing footprint area.
Solution Approach 2:
The patent embeds multiple conductive line levels within each other in a stacked configuration. Each conductive line level is nested between dielectric layers, and alternating levels are connected through vias to form interleaved electrode pairs, effectively nesting functional elements within a compact vertical structure to maximize capacitance within limited space.
2Quantity of substance
If interdigitated capacitor structure is used, then capacitance is increased through fringing and crossover capacitances, but crossover capacitances are limited to a single conductor level
Solution Approach 1:
The patent extends the interdigitated concept from a single plane to multiple vertical levels. By stacking conductive line levels and connecting alternating levels with vias, the structure creates multiple tiers of interdigitated electrodes, enabling fringing and crossover capacitances to occur across multiple conductor levels rather than being confined to a single level.
Solution Approach 2:
The patent divides the capacitor into multiple discrete conductive line levels separated by dielectric layers. Each level can be independently patterned and connected through vias, allowing the capacitance to be segmented across multiple levels. This segmentation enables cumulative capacitance from multiple interdigitated pairs while maintaining manufacturing flexibility.
3Quantity of substance
If vias are densely arranged during photolithography, then capacitance increases, but pattern transferring deviation occurs
Solution Approach 1:
The patent segments the via arrangement into distinct groups associated with different conductive line levels. By organizing vias to connect specific alternating levels rather than creating a uniform dense grid, the structure reduces via density in any single local region while maintaining overall high capacitance through the cumulative effect of multiple level connections.
Solution Approach 2:
The patent applies different via arrangement characteristics to different regions and levels. Vias are strategically placed to connect alternating conductive line levels, creating localized via densities that optimize capacitance while avoiding excessive density in any single area. This local optimization maintains photolithography precision while achieving high overall capacitance.
Data Source
AI summary
A capacitor structure includes a plurality of conductive line levels located over the substrate. Each of the conductive line levels includes a first conductive line and a second conductive line. The first conductive lines in the conductive line levels form a first conductive line co-plane and the second conductive lines in the conductive line levels form a second conductive line co-plane. A first conductive end is electrically connected to the first conductive lines on the conductive line levels. A second conductive end is electrically connected to the second conductive lines on the conductive line levels. A plurality of vias are located between the neighboring conductive line levels and placed on only one of the first and second conductive line co-planes on a same level.