Multilayer Masking Structure for Selective Semiconductor Etching
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Solution Overview
Problem
As semiconductor devices continue to reduce minimum feature sizes for increased integration density, challenges arise in efficiently patterning and processing semiconductor layers while maintaining precision and ease of removal of masking layers.
Innovation Solution
A method for forming multilayer masking layers that selectively etch semiconductor materials with high selectivity, allowing for precise patterning of nanostructures in p-type and n-type regions, followed by the formation of gate structures and interconnects, with the use of masking layers that facilitate easy removal.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If single-layer masking layers are used for patterning semiconductor materials, then the manufacturing process is simple, but the etching selectivity between different semiconductor materials (e.g., SiGe and Si) is insufficient, leading to poor patterning precision
Solution Approach 1:
The masking layer is divided into multiple sub-layers (first masking layer and second masking layer) with different materials and etching selectivities. The first masking layer provides initial pattern definition, while the second masking layer enhances selectivity for etching specific semiconductor materials like SiGe versus Si, thereby achieving superior patterning precision without excessive complexity
Solution Approach 2:
The masking structure uses composite materials with different etching selectivities - combining a first masking layer material (e.g., silicon nitride) with a second masking layer material (e.g., silicon oxide or different nitrogen-containing dielectric). This composite structure enables differential etching of SiGe and Si materials during nanowire formation, solving the selectivity problem
2Manufacturing precision
If masking layers are designed for high etching selectivity, then patterning precision is improved, but the removal of masking layers becomes difficult and time-consuming
Solution Approach 1:
The masking layers are designed with specific material parameters that provide high etching selectivity during patterning but also have controlled removal characteristics. By selecting materials and thicknesses appropriately, the masking layers can be selectively removed after serving their patterning function, reducing removal time while maintaining precision
Solution Approach 2:
The masking layers are configured to facilitate subsequent removal processes. The structure is designed in advance with materials and thicknesses that enable easy removal after patterning, such as using materials that can be selectively removed or have controlled adhesion properties, thereby reducing the time required for masking layer removal
3Productivity
If minimum feature sizes are reduced to increase integration density, then more components can be integrated, but patterning and processing challenges increase significantly
Solution Approach 1:
The patterning process is segmented into multiple steps using multiple masking layers, each with specific functions. This segmentation allows for precise control of nanoscale features by addressing different patterning requirements at different stages, making the complex process of forming small features more manageable and controllable
Solution Approach 2:
Composite masking structures with materials having different etching selectivities are used to enable precise patterning of alternating SiGe and Si nanowires at reduced feature sizes. The composite structure provides the necessary selectivity to define narrow features accurately, supporting higher integration density despite increased process complexity
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Enhances the efficiency of semiconductor device manufacturing by improving the precision and ease of processing, particularly in forming nano-FETs, while allowing for easier removal of masking layers, thus supporting higher integration densities.
Implementation Method 1
A method for forming multilayer masking layers that selectively etch semiconductor materials with high selectivity
Data Source
AI summary
A method includes forming a semiconductor layer over a substrate; etching a portion of the semiconductor layer to form a first recess and a second recess; forming a first masking layer over the semiconductor layer; performing a first thermal treatment on the first masking layer, the first thermal treatment densifying the first masking layer; etching the first masking layer to expose the first recess; forming a first semiconductor material in the first recess; and removing the first masking layer.