Multilayer Memory Junction Resistance Uniformity
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Solution Overview
Problem
The performance of multilayer memory circuits is affected by varying electrical properties of memory elements across different layers, leading to non-uniform internal voltages when an external voltage is applied, which impacts the overall performance.
Innovation Solution
The implementation of a three-dimensional architecture where memory elements are configured to have uniform junction resistance across layers, achieved by adjusting the thickness and resistivity of switching layers and conductive layers, ensuring uniform internal voltages across the multilayer structure for a given external voltage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If memory elements are stacked in multiple layers to increase planar density, then the planar density of integrated circuits is improved, but the electrical properties of memory elements vary depending on their position in the multilayer structure, leading to non-uniform internal voltages
Solution Approach 1:
The patent applies local quality by varying the resistance of switching layers in different memory elements based on their position within the multilayer structure. Memory elements closer to the voltage source are configured with higher resistance, while those farther away have lower resistance. This localized adjustment compensates for voltage drops in the conductive path, ensuring uniform internal voltages across all layers and positions.
Solution Approach 2:
The patent implements parameter changes by adjusting the resistance parameter of switching layers according to position. Specifically, the resistance values are modified to compensate for positional effects on voltage distribution. This parameter adjustment ensures that despite variations in conductive path length and resistance, all memory elements achieve uniform internal voltages for a given external applied voltage.
2Device complexity
If memory elements at different positions have different internal voltages, then the multilayer structure can be formed with varying conductive path resistances, but the performance of the memory circuit is degraded
Solution Approach 1:
The patent applies local quality by configuring switching layers with position-dependent resistance characteristics. Memory elements experiencing higher voltage drops due to longer conductive paths are equipped with switching layers that have optimized resistance values to compensate for this effect. This localized optimization maintains uniform operational conditions across all memory elements despite structural variations.
Solution Approach 2:
The patent implements preliminary anti-action by pre-configuring the resistance of switching layers to counteract the expected voltage drops in different positions before operation. By anticipating the voltage distribution issues that would arise from varying conductive path resistances, the design proactively compensates for these effects through carefully selected resistance values, preventing performance degradation before it occurs.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration ensures that memory elements across different layers operate at uniform internal voltages, enhancing the performance and planar density of integrated circuits by maintaining consistent electrical properties regardless of position within the multilayer structure.
Implementation Method 1
Memory elements at higher disposed positions are configured to have a higher overall resistance than memory elements at lower disposed positions so that the multilayer structure presents substantially uniform junction resistance across the memory elements
Data Source
AI summary
A multilayer structure is provided that includes a base and a multilayer circuit disposed above the base. The multilayer circuit includes memory elements, each including a switching layer, and conductive lines leading from the base to the memory element. The total resistance of the switching layer of a memory element is varied based on the total resistance of conductive lines leading from the base to the memory element.