Multi-Work Function Metal Gate for FinFET Threshold Tuning
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Solution Overview
Problem
Current FinFET architectures face challenges in adjusting threshold voltages, as conventional methods like ion implantation are ineffective, and polysilicon gates suffer from performance issues due to boron penetration and depletion effects, reducing gate capacitance and driving force.
Innovation Solution
A method involving a substrate with defined regions, a tuning layer, and multiple work function metal layers, along with a top and bottom barrier metal layer, is used to form a metal gate transistor, allowing for the creation of multi-threshold voltage regions through precise layer deposition and etching processes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If polysilicon gate is used, then gap-filling capability is achieved, but performance deteriorates due to boron penetration and depletion effect
Solution Approach 1:
The patent uses a composite gate structure consisting of multiple metal layers (e.g., tungsten, cobalt, titanium nitride) combined with high-k dielectric materials. This composite approach replaces the single-material polysilicon gate, achieving both the desired electrical performance and gap-filling capability through the synergistic properties of different materials.
Solution Approach 2:
The patent changes the work function parameters of the gate electrode by selecting metals with different work function values and controlling their thicknesses. By adjusting the composition and thickness of each metal layer, the effective work function can be tuned to achieve desired threshold voltages while maintaining good gap-filling properties.
2Device complexity
If conventional metal gate structure is used, then manufacturing simplicity is maintained, but multi-threshold voltage regions cannot be formed
Solution Approach 1:
The patent divides the gate electrode into multiple metal layers, each with different work function characteristics. By selectively depositing and etching these layers in different regions, distinct threshold voltage regions can be formed within a single gate structure. This segmentation approach maintains manufacturing simplicity by using sequential deposition and etching processes rather than requiring completely different fabrication techniques.
Solution Approach 2:
The patent implements local quality by creating spatial variations in the gate electrode composition. Different metal layers are present in different regions of the gate, allowing each region to have locally optimized electrical characteristics. This is achieved through selective area deposition or etching processes that modify the gate stack composition in specific device regions while leaving other regions unchanged.
Data Source
AI summary
A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate having a first region, a second region, a third region, and a fourth region; forming a tuning layer on the second region; forming a first work function metal layer on the first region and the tuning layer of the second region; forming a second work function metal layer on the first region, the second region, and the fourth region; and forming a top barrier metal (TBM) layer on the first region, the second region, the third region, and the fourth region.