Multilayer Printed Wiring Board Thermal Stress Reduction
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The existing printed wiring boards face challenges in mounting fine-pitch semiconductor chips due to limitations in wiring size and thermal stress caused by mismatches in coefficients of thermal expansion between silicon interposers and organic substrates, leading to potential connection failures during temperature cycle tests.
Innovation Solution
A printed wiring board with a multilayer structure comprising silicon layers and resin layers, where the thicknesses of both types of layers decrease alternately from the semiconductor chip side to the organic substrate side, matching the thermal expansion coefficients of both components, thereby reducing thermal stress and ensuring reliable connections.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If a silicon interposer is used to enable fine-pitch wiring formation, then wiring size and connection electrode pitch can be reduced, but thermal stress occurs due to mismatch in coefficients of thermal expansion between the silicon interposer and the organic substrate
Solution Approach 1:
The interposer is divided into multiple layers with different materials: a first interposer layer made of silicon (matching the semiconductor chip's thermal expansion coefficient) and a second interposer layer made of a material with intermediate thermal expansion properties. This segmentation allows each layer to handle different thermal expansion requirements, resolving the contradiction between fine-pitch capability and thermal stress.
Solution Approach 2:
The interposer uses a composite structure combining silicon and other materials (such as metal alloys or ceramics) in different layers. The silicon layer provides thermal expansion matching with the semiconductor chip, while the composite materials in the second layer provide thermal expansion matching with the organic substrate, thereby eliminating thermal stress while maintaining fine-pitch wiring capability.
2Reliability
If a special material with intermediate thermal expansion coefficient is used for the interposer, then thermal stress between the interposer and organic substrate is reduced, but the interposer cannot be formed using standard silicon fabrication techniques and manufacturing cost increases
Solution Approach 1:
The interposer is segmented into a first layer (silicon) that can be manufactured using standard silicon fabrication techniques and a second layer (composite material) that is applied subsequently. This allows the majority of the interposer to be produced using cost-effective silicon processes, while only a portion requires special materials.
Solution Approach 2:
The second interposer layer acts as an intermediary between the silicon first layer and the organic substrate. It mediates the thermal expansion mismatch by providing an intermediate thermal expansion coefficient, thereby reducing thermal stress without requiring the entire interposer to be made from expensive special materials.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration eliminates thermal stress at the interface between the semiconductor chip and the printed wiring board, and between the organic substrate and the printed wiring board, enhancing the reliability of semiconductor devices and allowing them to pass temperature cycle tests without connection failures.
Implementation Method 1
matching the thermal expansion coefficients of both components, thereby reducing thermal stress
Data Source
AI summary
A printed wiring board is configured to be connected to an organic substrate in a state where a semiconductor chip is mounted thereon. A plurality of first layers are formed of a material having the same coefficient of thermal expansion as the semiconductor chip. A plurality of second layers are formed of a material having the same coefficient of thermal expansion as the organic substrate. The first layers have different thicknesses from each other and the second layers have different thicknesses from each other. The first layers and the second layers form a lamination by being laminated alternately one on another. The thicknesses of the first layers decrease from a side where the semiconductor chip is mounted toward a side where the organic substrate is connected. The thicknesses of the second layers decrease from the side where the organic substrate is connected toward the side where the semiconductor chip is mounted.