Multilayer Redistribution Circuit Structure with Controlled Grain Size
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Solution Overview
Problem
The semiconductor industry faces challenges in efficiently forming redistribution circuit structures within integrated fan-out packages, which are crucial for compact packaging and high integration density, due to limitations in current fabrication processes that affect the reliability and yield of 3D packaging and 3DIC devices.
Innovation Solution
A method for fabricating integrated fan-out packages involves forming a redistribution circuit structure with a multilayer conductive via structure, where the conductive vias and redistribution layers are formed using a plating process with specific seed layers and photoresist patterns, and a dielectric layer that exposes conductive pillars and through vias, ensuring electrical connectivity and mechanical reliability through controlled grain size and plating density.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional fabrication processes are used for forming redistribution circuit structures, then manufacturing simplicity is maintained, but reliability and yield of 3D packaging are insufficient
Solution Approach 1:
The fabrication process is divided into multiple sequential plating steps, each forming a specific layer (seed layer, first conductive layer, second conductive layer) with controlled grain sizes. This segmentation allows precise control over each layer's properties to enhance reliability while managing overall process complexity through systematic breakdown.
Solution Approach 2:
The patent employs parameter changes by controlling grain size at different stages - forming a first grain size in the seed layer and a second grain size in the conductive layers. This parameter control during plating processes optimizes electrical connectivity and mechanical integrity, directly improving reliability of the redistribution circuit structure.
2Reliability
If conventional plating processes are used, then manufacturing simplicity is maintained, but electrical connectivity and mechanical integrity are insufficient
Solution Approach 1:
Different regions of the conductive structure are given different local qualities through controlled grain sizes - the seed layer has a first grain size while the conductive layers have a second grain size. This local quality differentiation optimizes both electrical connectivity in the conductive paths and mechanical integrity at interfaces, enhancing reliability without requiring entirely new manufacturing approaches.
Solution Approach 2:
The redistribution circuit structure uses a composite multilayer architecture combining seed layers and conductive layers with different grain size characteristics. This composite structure leverages the advantages of each layer - the seed layer provides nucleation control while the conductive layers provide optimized electrical and mechanical properties, achieving enhanced reliability through material composition rather than process simplification.
3Productivity
If simple package structures are used, then manufacturing simplicity is maintained, but integration density of semiconductor components is insufficient
Solution Approach 1:
The patent transitions from planar to three-dimensional packaging by forming vertical conductive vias and stacked conductive layers. This dimensional change enables higher integration density by utilizing the Z-axis for component interconnection, allowing multiple components to be stacked vertically while the complex plating process provides the necessary fine-pitch interconnect structure for 3D packaging.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances the reliability and yield of 3D packaging by ensuring robust electrical connectivity and mechanical integrity of the redistribution circuit structure, reducing the risk of cracks due to thermal cycling and improving the integration density of semiconductor components.
Implementation Method 1
a method for fabricating integrated fan-out packages involves forming a redistribution circuit structure with a multilayer conductive via structure, where the conductive vias and redistribution layers are formed using a plating process
Data Source
AI summary
A redistribution circuit structure electrically connected to a die underneath is provided. The redistribution circuit structure includes a dielectric layer and a conductive layer. The dielectric layer partially covers the die, so that a conductive pillar of the die is exposed by the dielectric layer. The conductive layer is disposed over the dielectric layer and electrically connected to the die by the conductive pillar. The conductive layer includes a multilayer structure, wherein an average grain size of one layer of the multilayer structure is less than or equal to 2 μm. A method of fabricating the redistribution circuit structure and an integrated fan-out package are also provided.