Multilayer RRAM Array Circuit for PUF Security
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Solution Overview
Problem
Current physical unclonable functions (PUFs) are vulnerable to machine learning algorithm attacks, which compromise their security in hardware authentication due to low data complexity and reuse of RRAM units, leading to predictable outputs.
Innovation Solution
A multilayer RRAM array circuit structure with address mapping methods between RRAM device arrays increases data complexity, enhancing resistance to machine learning algorithm attacks by uniquely mapping resistance values across layers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a single-layer RRAM array is used for PUF implementation, then the device complexity is low, but the data complexity is insufficient making it vulnerable to machine learning attacks
Solution Approach 1:
The patent transitions from a single-layer RRAM array to a multilayer RRAM array structure, adding the vertical dimension (layer stacking) to the existing horizontal array structure. This dimensional expansion increases the total number of RRAM units from a single layer to multiple layers, thereby increasing data complexity and security against machine learning attacks while maintaining reasonable device complexity through vertical integration
2Reliability
If RRAM units are reused across different outputs, then the productivity is high, but the outputs become predictable reducing security
Solution Approach 1:
The patent segments the RRAM units into distinct groups associated with different output bits. Each RRAM unit is dedicated to specific output positions rather than being reused across multiple outputs. This segmentation ensures that each output bit is generated from independent, non-reused RRAM units, making outputs unpredictable while maintaining efficient parallel generation across multiple bits
3Reliability
If the same operation voltage is applied to all RRAM devices, then the ease of operation is high, but the resistance values are not sufficiently differentiated reducing authentication security
Solution Approach 1:
The patent applies different operation voltages to different RRAM devices based on their specific resistance characteristics. Rather than using a uniform voltage for all devices, the system tailors the operation voltage to each RRAM device's local properties, ensuring sufficient resistance value differentiation for secure authentication while managing voltage control complexity through localized adjustment
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The proposed solution significantly improves the PUF's capability to resist machine learning algorithm attacks, enhancing the security of hardware authentication by increasing data complexity and uniqueness of outputs.
Implementation Method 1
the first address circuit is configured to map a resistance value of a second RRAM device in the second RRAM device array to a first address
Data Source
AI summary
A circuit structure for implementing a physical unclonable function and a driving method thereof, an integrated circuit chip and an authentication method thereof, an electronic device are disclosed. The circuit structure includes: a multilayer circuit, a first address circuit and an output circuit, the multilayer circuit includes a first RRAM device array which is addressable and a second RRAM device array which is addressable; the first address circuit is configured to map a resistance value of a second RRAM device in the second RRAM device array to a first address; the first address is used for positioning a selected first RRAM device; and the output circuit is configured to acquire and process a resistance value of the selected first RRAM device and output a processing result.