Multilayer Substrate with Hybrid Vias for Current Capacity
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Solution Overview
Problem
Existing multilayer substrates face challenges with long manufacturing processes and high costs due to high interlayer resistance values, which limit the allowable current capacity.
Innovation Solution
The proposed multilayer substrate incorporates interlayer coupling using both plated vias and conductive paste vias, with the paste vias not formed in a row in the lamination direction, to reduce interlayer resistance and increase current capacity. Additionally, the method involves manufacturing plated-via laminated bodies and laminating them with paste vias, which reduces the overall manufacturing process time.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of time
If interlayer coupling is achieved with conductive paste only, then the manufacturing process is short, but the interlayer resistance value is high
Solution Approach 1:
The patent combines two types of interlayer coupling methods: plated vias and conductive paste vias. The plated vias provide low resistance pathways for current flow, while the conductive paste vias maintain electrical connectivity between layers. This hybrid approach leverages the advantages of both methods to achieve both low interlayer resistance and reduced manufacturing time.
Solution Approach 2:
The patent employs a composite structure where both plated metal vias and conductive paste vias coexist within the multilayer substrate. This composite approach allows different materials to serve different functions: plated vias for low-resistance current paths and conductive paste vias for structural connectivity, thereby optimizing both electrical performance and manufacturing efficiency.
2Manufacturing precision
If multiple insulating bonding layers are disposed between all insulating layers, then the manufacturing precision is improved, but the manufacturing cost increases
Solution Approach 1:
Instead of uniformly disposing insulating bonding layers between all insulating layers, the patent applies bonding layers selectively only where necessary for maintaining layer alignment and structural integrity. This localized approach reduces the total number of bonding layers required, thereby lowering manufacturing costs while preserving the necessary precision for critical alignments.
Solution Approach 2:
The patent extracts or removes unnecessary insulating bonding layers from the overall structure. By identifying and eliminating redundant bonding layers that do not contribute to critical alignment functions, the patent reduces manufacturing complexity and cost while maintaining sufficient manufacturing precision through the remaining strategically placed bonding layers.
3Ease of manufacture
If paste vias are formed in a row in lamination direction, then the manufacturing process is simplified, but the interlayer resistance value increases
Solution Approach 1:
The patent employs an asymmetric arrangement where paste vias are not aligned in a straight row along the lamination direction. Instead, they are positioned in a distributed pattern that creates multiple current pathways. This asymmetric configuration increases the effective conductive area and reduces current density in any single location, thereby lowering interlayer resistance while maintaining manufacturing simplicity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration effectively decreases interlayer resistance, thereby increasing the allowable current value and reducing manufacturing costs by shortening the process time and minimizing the use of insulating bonding layers.
Implementation Method 1
a first through hole penetrating the first insulating layer up to an obverse surface of the first plating pattern to thereby couple the first plating pattern and the second plating pattern with a plated via obtained by plating the first through hole
Implementation Method 2
a second through hole penetrating the second insulating layer up to an obverse surface of the second plating pattern in any of the plurality of the plated-via laminated bodies, a step of filling the second through hole with a conductive paste
Implementation Method 3
a step of electrically coupling the metal layers opposed to each other with a paste via filled with a conductive paste to laminate the plurality of the plated-via laminated bodies
Data Source
AI summary
To shorten a manufacturing process and to decrease an interlayer resistance value to thereby increase an allowable current value are set as problems. As means for solving the problems, in a multilayer substrate (20) which includes a plurality of insulating layers (24) and a plurality of metal layers (12) formed on both surfaces of the insulating layers (24) and patterned, and in which the metal layers (12), (12) are interlayer-coupled to each other with vias, there are included layers which are interlayer-coupled to each other with plated vias (14), and layers which are interlayer-coupled to each other with paste vias (16) filled with a conductive paste.