Multilayer Substrate Via Layout for Low-Resistance High-Frequency Signals
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Solution Overview
Problem
Conventional multilayer substrates have high resistance, which hinders efficient transmission of high-frequency signals.
Innovation Solution
A multilayer substrate design with aligned interlayer connection conductors in specific rows along signal conductors, differing in position and direction, to reduce resistance and enhance signal transmission.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If conventional multilayer substrates are used with simple signal conductor connections, then the structure is simple, but the resistance is high which hinders efficient high-frequency signal transmission
Solution Approach 1:
The patent divides the interlayer connection into multiple separate connection conductors arranged in parallel rows, rather than using a single connection path. This segmentation creates multiple current paths between signal conductors on different layers, reducing overall resistance while maintaining a manageable structural complexity through systematic arrangement.
Solution Approach 2:
The patent transitions from simple planar connections to three-dimensional stacked connections across multiple layers. By arranging connection conductors in multiple rows at different positions in the lamination direction and utilizing overlapping signal conductors on different layers, the invention creates additional spatial dimensions for current flow, effectively reducing resistance without excessive structural complexity.
2Loss of energy
If multiple interlayer connection conductors are added to reduce resistance, then the resistance decreases, but the manufacturing complexity increases
Solution Approach 1:
The patent combines multiple connection conductors into organized parallel rows that can be manufactured as integrated structures. By merging the functions of multiple individual connections into a systematic row-based arrangement, the invention reduces resistance through multiple parallel paths while simplifying the manufacturing process through standardized, repeatable patterns that can be produced using conventional multilayer PCB techniques.
Solution Approach 2:
The patent optimizes geometric parameters such as the spacing between connection conductors in rows, the distance between rows, and the overlap positioning of signal conductors. By carefully controlling these parameters, the invention achieves optimal resistance reduction while maintaining manufacturability within standard manufacturing tolerances and process capabilities.
3Loss of energy
If connection conductors are positioned to maximize overlap and reduce resistance, then resistance decreases, but parasitic capacitance increases
Solution Approach 1:
The patent applies different spatial arrangements to different regions of the connection structure. By positioning connection conductors in specific row configurations and controlling their lateral displacement relative to signal conductors, the invention creates optimal local electric field distributions that reduce resistance while minimizing parasitic capacitance through careful spatial management of conductive elements.
Solution Approach 2:
The patent utilizes the lamination direction (vertical dimension) to separate connection conductors into multiple rows at different heights, reducing lateral proximity and thus parasitic capacitance between conductors. Simultaneously, the overlapping signal conductors on different layers provide vertical current paths that reduce resistance, effectively decoupling the resistance and capacitance trade-off through three-dimensional spatial arrangement.
Data Source
AI summary
In a multilayer substrate, first interlayer connection conductors pass through resin layers in a lamination direction and electrically connect first and second signal conductors. Second interlayer connection conductors pass through the resin layers in the lamination direction and electrically connect the first and second signal conductors. The first interlayer connection conductors are aligned in a first row extending along the first signal conductor when viewed in the lamination direction. The second interlayer connection conductors are aligned in a second row extending along the first signal conductor when viewed in the lamination direction. A direction perpendicular to the direction in which the first signal conductor extends, when viewed in the lamination direction, is a line width direction. A position of the second row in the line width direction is different from a position of the first row in the line width direction.