Multilayer Wiring Substrate for Fine Pitch Interposer
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Solution Overview
Problem
The increasing demand for high-specification interposers with high bandwidth memory has led to increased process complexity, resulting in lower yields and adhesive force issues between microcircuit patterns and insulating materials, particularly with silicon interposers, which limits the formation of microcircuit patterns with fine pitches.
Innovation Solution
A printed circuit board design that includes a microcircuit pattern formed on a multilayer wiring substrate by attaching a microcircuit board manufactured through a separate process, using an embedded trace substrate method, which avoids the undercut issue and maintains sufficient adhesive force, replacing the need for silicon interposers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If a silicon interposer is used with high bandwidth memory, then the wiring density and performance are improved, but the process complexity increases and yield decreases
Solution Approach 1:
The patent changes the material parameter from silicon to organic insulating material, and changes the manufacturing process parameters to use standard PCB techniques instead of complex semiconductor processes. This allows achieving high wiring density through multilayer construction without requiring complex silicon processing techniques
Solution Approach 2:
The patent replaces expensive silicon interposers with cost-effective organic-based multilayer wiring substrates. The organic material approach uses readily available, inexpensive materials and standard manufacturing processes, eliminating the need for costly silicon fabrication facilities
2Quantity of substance
If a microcircuit pattern with fine pitch is formed on silicon interposer, then the wiring density is improved, but the adhesive force between microcircuit pattern and insulating material decreases
Solution Approach 1:
The patent uses composite material structures with organic insulating layers combined with metal wiring layers. The organic insulating material provides excellent adhesion to the metal patterns, and the multilayer composite construction enables fine pitch wiring while maintaining strong bonding between layers through standardized adhesive interfaces
Solution Approach 2:
The patent changes the insulating material from silicon to organic materials that provide better adhesive properties. The organic insulating layers are specifically selected to ensure strong bonding with metal wiring patterns, resolving the adhesion problem that occurs with silicon-based approaches
3Power
If the number of HBMs is increased for high specification, then the performance is improved, but the process difficulty increases and yield decreases
Solution Approach 1:
The patent segments the interposer function into multiple separate organic insulating layers, each containing subsets of the wiring patterns. This segmentation allows each layer to be manufactured using standard PCB processes with lower difficulty, while the cumulative effect of multiple layers achieves the required high wiring density and performance
Solution Approach 2:
The patent creates a universal multilayer wiring substrate that can accommodate multiple HBMs and various electronic components through standardized mounting interfaces. The organic-based substrate provides universal compatibility with different component types and configurations, simplifying the manufacturing process for high-specification assemblies
Data Source
AI summary
A printed circuit board includes a first wiring structure including first insulating layers and first wiring layers; a second wiring structure disposed on the first wiring structure and including second insulating layers and second wiring layers; and a third wiring structure disposed on the second wiring structure and including a third insulating layer and a third wiring layer disposed on the third insulating layer. At least a portion of at least one of the second wiring layers has a fine pitch, relatively finer than those of the first wiring layers and the third wiring layer, wherein at least a portion of one of the first wiring layers is connected to at least a portion of the third wiring layer through a first wiring via, and wherein the first wiring via penetrates at least one of the first insulating layers, the second insulating layers, and the third insulating layer.