Multilayered Chip Capacitor Non-Conductive Layer Solder Overflow

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Solution Overview

Problem

Multilayered chip capacitors generate acoustic noise when voltage is applied due to vibrations transferred to the printed circuit board, causing discomfort, and existing solutions do not effectively prevent solder overflow or reduce noise.

Innovation Solution

A multilayered chip electronic component with non-conductive layers on its side surfaces and specific plating layers to reduce solder height and prevent overflow, combined with a board design that minimizes solder fillet height to decrease acoustic noise.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If solder fillet height is increased to ensure reliable soldering connection, then soldering reliability is improved, but acoustic noise increases due to vibration transfer

Engineering Contradiction:
Improvesoldering reliabilityVSAvoidacoustic noise
Core Design Contradiction:
ReliabilityVSObject-generated harmful factors

Solution Approach 1:

A non-conductive layer is introduced as an intermediary between the plating layer and the external electrode. This layer acts as a vibration isolation barrier that blocks the transmission path from solder fillet vibrations to the internal electrodes, thereby reducing acoustic noise while maintaining adequate solder fillet height for reliable connections

Inventive Principle:
Principle #24Intermediary (Mediator)

Solution Approach 2:

The non-conductive layer is pre-positioned between the plating layer and external electrode to provide cushioning against vibration transfer before the soldering process occurs. This preventive measure ensures that even with taller solder fillets needed for reliable soldering, the vibration energy is dampened before reaching the sensitive internal electrodes

Inventive Principle:
Principle #11Beforehand cushioning (Prior cushioning)

2Reliability

If plating layer thickness is increased to prevent solder overflow, then solder overflow prevention is improved, but manufacturing complexity increases

Engineering Contradiction:
Improvesolder overflow preventionVSAvoidmanufacturing complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The non-conductive layer serves as a physical barrier and intermediary structure that limits the lateral flow of solder. By positioning this layer between the plating layer and external electrode, solder overflow is prevented without requiring excessive plating thickness, thus simplifying the manufacturing process

Inventive Principle:
Principle #24Intermediary (Mediator)

Solution Approach 2:

The non-conductive layer is applied selectively in specific regions where solder overflow is most likely to occur. This localized approach provides effective solder containment while avoiding the need to increase plating thickness across the entire component, reducing manufacturing complexity

Inventive Principle:
Principle #3Local quality

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

Significantly reduces acoustic noise by minimizing solder fillet height and preventing solder overflow, enhancing the reliability of the mounting process and reducing listener discomfort.

Implementation Method 1

non-conductive layers formed on outer side surfaces of the first plating layers

Methodology Applied
Scientific EffectPhysical barrier:

Implementation Method 2

a piezoelectric phenomenon and vibrations are generated between the internal electrodes

Methodology Applied
Scientific EffectPiezoelectric phenomenon: Piezoelectric Effect

Implementation Method 3

a solder fillet fixing the multilayered chip capacitor to the printed circuit board

Methodology Applied
Scientific EffectSoldering: Soldering

Data Source

PatentUS9439301B2Multilayered chip electronic component and board for mounting the same
Publication Date: 2016.09.06 SAMSUNG ELECTRO MECHANICS CO LTD
  • US9439301B2 patent drawing
  • US9439301B2 patent drawing
  • US9439301B2 patent drawing

AI summary

There is provided a multilayered chip electronic component including: a ceramic body including internal electrodes and dielectric layers; external electrodes covering both end surfaces of the ceramic body in a length direction; first plating layers forming the external electrodes and formed on outer surfaces of the ceramic body; non-conductive layers formed on outer side surfaces of the first plating layers; and second plating layers formed on regions of the first plating layers except for the non-conductive layers.