Multi-Layered SiGe Source/Drain for Vertical FETs
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The increasing demand for high-performance, high-speed, and multifunctional semiconductor devices has led to challenges in achieving improved electrical properties, particularly due to the limitations imposed by the reduction in size of planar metal oxide semiconductor FETs.
Innovation Solution
The semiconductor device incorporates a gate-all-around type field effect transistor structure with a multi-bridge channel FET configuration, featuring a plurality of channel layers with a three-dimensional channel structure, and a source/drain region with multiple epitaxial layers having varying germanium concentrations to enhance electrical performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the size of planar metal oxide semiconductor FET is reduced to increase integration density, then integration density is improved, but electrical properties deteriorate
Solution Approach 1:
The patent transitions from a planar 2D channel structure to a three-dimensional FinFET structure with vertical channels extending in the depth direction. This dimensional change allows the device to maintain effective channel width and electrical performance while reducing the planar footprint, thereby achieving higher integration density without sacrificing electrical properties.
Solution Approach 2:
The channel region is segmented into multiple fins or ridges that extend vertically from the substrate. This segmentation creates multiple parallel conduction paths within a compact area, increasing the effective channel width and improving electrical characteristics while maintaining small device footprint for high integration density.
2Reliability
If multi-layered epitaxial structures are added to improve electrical properties, then charge mobility is improved, but device complexity increases
Solution Approach 1:
Different epitaxial layers are introduced with specific material compositions and doping profiles tailored to local requirements within the source/drain region. The first epitaxial layer provides lattice matching to reduce dislocation, while the second layer introduces stress to enhance charge mobility in the channel, optimizing local properties to improve overall device performance without excessive complexity.
Solution Approach 2:
The source/drain region employs a composite structure with multiple epitaxial layers having different material compositions and properties. This composite approach combines the advantages of each layer - dislocation reduction from the first layer and stress-induced mobility enhancement from the second layer - achieving superior electrical characteristics while managing structural complexity through systematic design.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration improves the electrical properties of the semiconductor device by reducing dislocation in the source/drain region, thereby enhancing charge mobility and reducing resistance in the channel layers, leading to improved device performance.
Implementation Method 1
a first epitaxial layer which extends on the active region and contacts the plurality of channel layers, and has a first upper surface that is configured to be recessed, and a second epitaxial layer which is in contact with a first portion of the first upper surface of the first epitaxial layer
Data Source
AI summary
A semiconductor device includes a semiconductor active region having a vertical stack of multiple spaced-apart semiconductor channel regions thereon. A gate electrode extends on the active region and between the spaced-apart channel regions. A source/drain region contacts the spaced-apart channel regions. The source/drain region includes a stack of at least first, second and third epitaxial layers having different electrical characteristics. The first epitaxial layer contacts the active region and each of the spaced-apart channel regions. The second epitaxial layer contacts a first portion of an upper surface of the first epitaxial layer. The third epitaxial layer contacts a second portion of the upper surface of the first epitaxial layer. Each of the first, second and third epitaxial layers includes silicon germanium (SiGe) with unequal levels of germanium (Ge) therein. A level of germanium in the third epitaxial layer exceeds a level of germanium in the second epitaxial layer, which exceeds a level of germanium in the first epitaxial layer.