Multilevel Cache Architecture with Exclusive Ranges
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Solution Overview
Problem
Conventional multilevel cache architectures in embedded systems face challenges due to the large size and coherence requirements of level-two (L2) caches, leading to increased complexity and cost, as well as inefficiencies when accessed by multiple hardware masters, resulting in higher cache misses and data replacement issues.
Innovation Solution
A processing module with a multilevel cache architecture that includes a level-one (L1) cache for the processor and a level-two (L2) cache for both processor and hardware engines, with mutually exclusive cacheable ranges and a memory interface for data transfer, utilizing single and burst transfer bus protocols to optimize data access and reduce latency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the L2 cache size is increased to improve data caching capacity, then the cache hit rate improves, but the cost and complexity of the system increases
Solution Approach 1:
The patent segments the cache system into L1 and L2 caches with mutually exclusive cacheable ranges. The L1 cache handles processor-specific data while the L2 cache handles hardware engine data, preventing coherence complexity while maintaining high hit rates for each domain.
Solution Approach 2:
The patent applies local quality by giving different cacheable ranges to L1 and L2 caches based on their specific needs. The L1 cache is optimized for processor access patterns while the L2 cache is optimized for hardware engine access patterns, allowing each cache to be sized and configured independently for its specific workload.
2Adaptability or versatility
If the L2 cache is made accessible to multiple hardware masters (DMA, hardware engines) to improve system versatility, then adaptability improves, but cache effectiveness deteriorates due to increased cache misses and data replacement
Solution Approach 1:
The patent segments the cache address space into mutually exclusive ranges: L1 cacheable ranges for the processor and L2 cacheable ranges for hardware engines. This segmentation allows multiple masters to access the cache system simultaneously without interfering with each other's data, maintaining cache effectiveness while providing versatile access.
Solution Approach 2:
The patent applies local quality by configuring different cacheable ranges for different masters. The L1 cache is configured with ranges suitable for processor access while the L2 cache is configured with ranges suitable for hardware engine access, allowing each master to access optimized data regions without causing unnecessary cache misses or replacements.
3Device complexity
If the L1 cacheable range and L2 cacheable range are made mutually exclusive to simplify cache design, then device complexity is reduced, but the cache coverage area is limited
Solution Approach 1:
The patent segments the total address space into multiple non-overlapping cacheable ranges, with L1 cacheable ranges dedicated to processor access and L2 cacheable ranges dedicated to hardware engine access. This segmentation simplifies the coherence model while allowing the system to scale coverage by adding more segmented ranges as needed.
Solution Approach 2:
The patent resolves the coverage limitation by extending the solution into another dimension: multiple hardware engines can each have their own L2 cacheable ranges, and multiple DMA controllers can access the L2 cache. This allows the cache coverage area to expand without increasing L1-L2 coherence complexity, as each engine operates in its own address space segment.
Data Source
AI summary
A processing module with multilevel cache architecture, including: a processor; a level-one (L1) cache, coupled to the processor, for caching data for the processor, wherein the L1 cache has at least one L1 cacheable range; a level-two (L2) cache, coupled to the L1 cache, for caching data for the processor, wherein the L2 cache has at least one L2 cacheable range, and the L1 cacheable range and the L2 cacheable range are mutually exclusive; and a memory interface, coupled to the L1 cache and the L2 cache, for transferring data between the L1 cache and a memory and for transferring data between the L2 cache and the memory.