Memory Systems TRIZ Cases
- Storage System Logical Unit Takeover and Data Migration
Autonomous logical unit takeover and data migration reduce maintenance complexity by eliminating manual administrator intervention during storage expansion.
- Tiering-Aware Data Defragmentation for Storage Arrays
A tiering-aware defragmentation system establishes storage zones to optimize block placement across multiple tiers.
- Dynamic Priority Arbitration for Fair Bus Access
A high fairness arbiter adjusts port priorities based on stall history to resolve bus access conflicts.
- OPROM Data Structure for Dynamic Firmware Image Updates
An OPROM data structure manages firmware images by dynamically updating identifiers based on hardware configuration changes.
- Memory Controller Buffering for Flash Write Performance
A memory controller buffers small host data units in temporary blocks before writing larger area data to nonvolatile memory.
- Mixed Memory Types Using Segmented Power Domains
Segmenting power domains with dedicated voltage regulators and clock oscillators allows diverse memory types in one system without interference.
- Fast On-Chip RAM Code Execution Optimization
Merges object heap with code cache to copy compiled methods into fast on-chip RAM, reducing fragmentation while maintaining speed.
- L1 Cache Arbitration for Multithreaded Clients
An L1 cache arbitrates concurrent requests from multiple clients by inserting bubbles into the request stream to grant access without stalling.
- Program Arrangement Method for Instruction Cache Conflict Reduction
Segments functions into cache line-sized blocks and calculates neighborhood weights based on call relations to reduce instruction cache conflicts.
- Coherence Planes for Chip Multi-Threaded Processor Interconnects
Segmenting interconnect traffic into independent coherence planes resolves bandwidth and latency bottlenecks in chip multi-threaded systems.
- Vector Register Parallel Processing for Character Data Length Determination
Parallel vector register loading determines character data length, preventing spurious exceptions from boundary crossings and reducing execution time.
- RAID-5 Controller Data Stream Distribution and Aggregation
A RAID-5 controller distributes data streams into sub-streams for parallel processing using dedicated transmission controllers.
- Dynamic Binary Translator Native Code Binding Control
A dynamic binary translator executes native code for performance while retaining execution control within the translation layer.
- Memory Controller Out-of-Order Chunk Access for Coherency Bottlenecks
A memory controller splits host commands into chunks and evaluates dependencies to submit independent data immediately.
- Centralized Registry Key Federation for Automated Reinstallation
Centralized database replication of registry keys automates reinstallation, eliminating manual tracking errors during system rebuilding.
- Transactional Distributed Runtime for Speculative Computation
A distributed runtime executes speculative transactions on shared datasets to accelerate parallel processing across computing clusters.
- Concatenated RAID 0 Architectures for Disk Capacity Utilization
Concatenating multiple RAID 0 groups utilizes remnant disk capacity, resolving underutilization in mixed-size arrays.
- Router-Based Storage Migration Preserving Thin Provisioning
A router migrates data between storage devices by detecting zero blocks to maintain thin provisioning.
- Cache Agent Eviction Priority Management for SoC Interoperability
Agent circuitry manages eviction and probe operation priorities to enable seamless interoperability between diverse cache coherence policies.