Program Arrangement Method for Instruction Cache Conflict Reduction
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Solution Overview
Problem
Existing methods for reducing instruction cache conflicts in computer systems with small cache capacities are ineffective as they do not consider the granularity of cache line units, leading to frequent conflicts and slower program execution.
Innovation Solution
The method involves dividing functions into instruction code blocks equal to the cache line size, tracing call relations to create flow information, and calculating neighborhood weights to optimize the arrangement of functions in memory space, thereby minimizing cache conflicts.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If functions are arranged in memory space without considering cache line granularity, then the arrangement process is simple, but instruction cache conflicts occur frequently
Solution Approach 1:
The patent segments functions into instruction code blocks with sizes matching cache line units. This segmentation allows the arrangement method to consider cache line granularity, preventing instruction cache conflicts while maintaining systematic organization. The segmentation transforms the arrangement problem from function-level to cache-line-level, resolving the contradiction between arrangement simplicity and execution efficiency.
Solution Approach 2:
The patent changes the arrangement parameters from function-level metadata to cache line-level details including instruction code block sizes and addresses. By introducing neighborhood weight calculations based on call relations and cache line characteristics, the arrangement process optimizes for cache performance without excessive complexity, improving program execution speed.
2Productivity
If functions with high call frequency are arranged together to reduce conflicts, then cache line utilization improves, but memory space arrangement complexity increases
Solution Approach 1:
The patent introduces neighborhood weight as a feedback mechanism that quantifies call relations between functions. This feedback allows the arrangement method to systematically identify and prioritize high-call-frequency function pairs, arranging them to share cache lines effectively. The feedback-driven approach improves cache line utilization while keeping arrangement complexity manageable through automated calculation.
Solution Approach 2:
The patent transforms qualitative call relation information into quantitative neighborhood weight parameters. This parameter transformation enables systematic arrangement decisions based on calculated weights rather than heuristic methods, improving cache utilization efficiency while maintaining consistent and reproducible arrangement results.
3Productivity
If instruction code blocks are divided to match cache line size, then cache conflict reduction becomes effective, but program division and arrangement complexity increases
Solution Approach 1:
The patent segments programs into instruction code blocks with sizes precisely matching cache line units. This segmentation is performed systematically based on instruction boundaries and call relation analysis, making the division process structured rather than arbitrary. The segmentation enables effective cache conflict reduction by ensuring each block maps to a single cache line, preventing conflicts while managing division complexity through systematic rules.
Solution Approach 2:
The patent creates a universal arrangement method that works across different programs and cache configurations by using standardized cache line size matching. This universal approach handles program division systematically, applying the same principles regardless of program structure, thereby reducing cache conflicts effectively while keeping division complexity manageable through consistent methodology.
Data Source
AI summary
For a program that is made up of functions in units, each function is divided into instruction code blocks having a size CS where CS is the instruction cache line size of a target processor and an instruction code block that is Xth counting from the top of each function F is expressed as (F, X). Flow information of nodes that take (F, X) as identification names is extracted from an executable file of the function program. For each identification name, as neighborhood weight of each identification name that differs from that identification name, information for which that the frequency of appearance of each identification name is taken into consideration that belongs to a function that differs from that function in the neighborhood of each appearing node in the flow information is found. Based on said neighborhood weight information, the functions are arranged in the memory space such that the number of conflicts of said instruction cache is reduced.