Multi-level Cell Programming via Concurrent Sub-block Voltage Conditioning
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Solution Overview
Problem
Current memory devices face inefficiencies in programming operations due to the need for multiple pulses to program multiple levels and sub-blocks, leading to increased latency and longer programming times.
Innovation Solution
Implementing a multi-level multi-sub-block programming method where a single programming pulse is applied concurrently to multiple sub-blocks, using a boost voltage to condition pillar channel voltages, allowing for simultaneous programming of different logical states across multiple sub-blocks.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If multiple programming pulses are applied to program multiple levels and sub-blocks sequentially, then programming completeness is achieved, but programming time and latency increase
Solution Approach 1:
The patent merges multiple programming operations into a single programming pulse by applying the pulse simultaneously to multiple sub-blocks. The boost voltage is applied to multiple sub-blocks concurrently, and a single programming pulse programs multiple levels across multiple sub-blocks at once, eliminating the need for sequential pulse applications and significantly reducing programming time while maintaining complete programming of all required memory cells
Solution Approach 2:
The patent applies boost voltage to multiple sub-blocks in advance before the actual programming pulse is applied. This preliminary action conditions the pillar channel voltages across multiple sub-blocks simultaneously, preparing them for concurrent programming. By performing this preparatory step beforehand, the system enables subsequent single-pulse programming of multiple levels and sub-blocks without requiring multiple sequential programming cycles
2Manufacturing precision
If multiple programming operations are performed sequentially for different sub-blocks, then all data is programmed accurately, but the number of program operations increases
Solution Approach 1:
The patent combines multiple programming operations into a single concurrent operation by applying boost voltage to multiple sub-blocks simultaneously and then applying one programming pulse that affects multiple levels across multiple sub-blocks at the same time. This merging approach maintains accurate programming of all data while dramatically increasing programming throughput by eliminating the sequential nature of traditional multi-step programming operations
Solution Approach 2:
The programming pulse serves multiple functions simultaneously by programming different levels (e.g., upper and lower pages) across multiple sub-blocks in a single operation. This multi-functionality allows the system to achieve complete data programming across the entire memory array with fewer operations, improving both accuracy and throughput
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces the number of program operations and latency by enabling concurrent programming of multiple levels and sub-blocks, improving overall memory device performance.
Implementation Method 1
a boost voltage is applied one or more times to condition pillar channel voltages for the plurality of sub-blocks
Data Source
AI summary
Control logic in a memory device causes a boost voltage to be applied one or more times to a plurality of unselected wordlines of a block of the memory array, the block comprising a plurality of sub-blocks, and the boost voltage to boost a channel potential of each of the plurality of sub-blocks by an amount each time the boost voltage is applied. The control logic further selectively discharges the amount of boost voltage from one or more of the plurality of sub-blocks after each time the boost voltage is applied according to a data pattern representing a sequence of bits to be programmed to respective memory cells of the plurality of sub-blocks. Additionally, the control logic causes a single programming pulse to be applied to one or more selected wordlines of the block to program the respective memory cells of the plurality of sub-blocks according to the data pattern.