Multilevel Leadframe Triple Etch Process for Flip Chip Bump Density
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Solution Overview
Problem
Current leadframe manufacturing capabilities limit the density of solder bumps in flip chip packages due to the space required for routing lead wires through bond pads, restricting the minimal pitch that can be fabricated.
Innovation Solution
A multilevel leadframe is fabricated using a triple etch process, allowing lead lines to be formed on a lower level while bond pads are on an upper level, reducing the clearance distance and enabling closer spacing of bond pads, thus accommodating more bumps in an array pattern.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If lead wires are routed through bond pads in a single layer, then the manufacturing process is simple, but the density of solder bumps is limited due to required clearance distances
Solution Approach 1:
The patent transitions from a single-layer leadframe structure to a multilevel structure by adding vertical dimensionality. Lead lines are formed on a lower level while bond pads are positioned on an upper level, allowing solder bumps to be placed closer together without requiring large clearance distances in the planar direction. This dimensional change enables higher bump density while maintaining manufacturability.
2Quantity of substance
If bond pads are spaced closer together to increase bump density, then more bumps can be accommodated, but the clearance distance for lead wire routing becomes insufficient
Solution Approach 1:
By separating lead lines and bond pads into different vertical levels, the patent eliminates the need for large planar clearance distances. The lead lines on the lower level can route beneath or near bond pads on the upper level without requiring lateral spacing, enabling bond pads to be positioned much closer together while maintaining adequate clearance for lead wire formation.
Solution Approach 2:
The leadframe structure is segmented into multiple levels with distinct functional zones. The lower level accommodates lead lines for routing, while the upper level is dedicated to bond pads for solder bump attachment. This segmentation allows each element to be optimized independently without interfering with the other, resolving the clearance distance constraint.
Data Source
AI summary
A method for forming a multilevel leadframe for an integrated circuit is provided. A conductive sheet is etched from one side to form a thinner region within a frame region for leads lines and bond pads. The conductive sheet is etched to form a plurality of bond pads in a first level of the thinner region arranged in at least a first row and a second row. Each bond pad has a pad width and is separated from an adjacent bond pad by a bond pad clearance distance. The conductive sheet is etched from an opposite side to form a plurality of lead lines in a second level of the thinner region having a line width and is separated from an adjacent lead line by at least a lead line clearance distance. Each bond pad of the second plurality of bond pads is connected to one of the plurality of lead lines on the second level that is routed between adjacent bond pads in the first row, so that the lead lines are routed on a different level from the bond pads.