Multimodal Nanosheet Transistor Integration With Dual-Gate Linear Response
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Solution Overview
Problem
Existing semiconductor processes for fabricating leading edge FET devices have not been integrated with multimodal transistor (MMT) device fabrication processes due to challenges in meeting performance requirements and cost constraints, particularly in integrating MMT devices with nanosheet transistors, which require metal source/drain regions and high operating voltages, leading to increased circuit size and wiring costs.
Innovation Solution
A method is developed to integrate multimodal transistors with thin film FET devices using a single fabrication process flow, incorporating buried metal source/drain structures and separate gate electrodes to achieve a linear drain current response, utilizing existing nanosheet transistor fabrication steps without requiring new fab tools.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If conventional TFT designs with single gate electrode are used, then fabrication process is simple, but drain current has quadratic response to gate voltage which is not suitable for computational approaches
Solution Approach 1:
The gate electrode is segmented into two independent gates (first gate and second gate) that can independently control different aspects of current flow. This segmentation enables the device to achieve linear transfer characteristics suitable for computational approaches while maintaining compatibility with standard fabrication processes.
Solution Approach 2:
The multimodal transistor design provides multi-functionality by enabling both linear transfer characteristics for computational approaches and compatibility with standard TFT fabrication processes. The device can operate in different modes depending on gate voltage application, achieving universality in application scenarios.
2Adaptability or versatility
If MMT device circuit elements are incorporated into existing FET fabrication processes, then linear drain current response is achieved, but device complexity and fabrication difficulty increase
Solution Approach 1:
The device structure is segmented with separate first and second gate electrodes positioned at different locations, allowing independent control of charge injection and current flow. This segmentation achieves linear transfer characteristics while the gates can be formed using standard multi-layer deposition and patterning processes.
Solution Approach 2:
The dual-gate structure adds a dimensional aspect to the device architecture, with gates positioned in different spatial locations (one at the channel entrance, one at the exit). This dimensional arrangement enables linear current response while maintaining compatibility with planar fabrication processes.
3Adaptability or versatility
If MMT devices are fabricated on silicon with large dimensions and high operating voltages, then linear drain current response is achieved, but integration with leading edge FET processes becomes difficult
Solution Approach 1:
The device is designed to operate with adjusted voltage parameters and dimensional scaling compatible with leading edge FET process nodes. By optimizing gate lengths, channel dimensions, and operating voltages to match standard process capabilities, linear transfer characteristics are achieved without requiring large dimensions or high voltages.
Solution Approach 2:
The multimodal transistor is designed to be universal in its compatibility with existing semiconductor fabrication processes. The device can be fabricated using standard process steps including deposition, etching, and doping, enabling integration with leading edge FET processes while maintaining linear transfer characteristics.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This integration method allows for the fabrication of MMT devices alongside nanosheet transistors on a single die, maintaining performance while minimizing additional costs and circuit size, enabling linear drain current response suitable for artificial intelligence applications.
Implementation Method 1
epitaxially growing a semiconductor channel layer
Data Source
AI summary
A semiconductor device and fabrication method are described for integrating a nanosheet transistor with a multimodal transistor (MMT) in a single nanosheet process flow by processing a wafer substrate to form buried metal source/drain structures in an MMT region that are laterally spaced apart from one another and positioned below an MMT semiconductor channel layer before forming a transistor stack of alternating Si and SiGe layers in an FET region which are selectively processed to form gate electrode openings so that a first ALD oxide and metal layer are patterned and etched to form gate electrodes in the transistor stack and to form a channel control gate electrode over the MMT semiconductor channel layer, and so that a second oxide and conductive layer are patterned and etched to form a current control gate electrode over the MMT semiconductor channel layer and adjacent to the channel control gate electrode.