Multimodal Transistor Integration in Nanosheet FET Process Flow
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Solution Overview
Problem
Existing semiconductor processes for fabricating leading edge FET devices have not been integrated with multimodal transistor (MMT) device fabrication processes due to challenges in meeting performance requirements and cost constraints, particularly in integrating MMT devices with nanosheet transistors, which require metal source/drain regions and high operating voltages, leading to increased circuit size and wiring costs.
Innovation Solution
A method is developed to integrate MMT devices with thin film FET devices using a single fabrication process flow, utilizing existing nanosheet transistor semiconductor fabrication steps to form buried metal source/drain structures, separate gate electrodes, and additional MMT control gates, allowing for a linear drain current response without requiring new fab tools.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If conventional TFT designs with single gate electrode are used, then device fabrication is simple, but transfer characteristics are not suitable for computational approaches requiring linear drain current response
Solution Approach 1:
The single gate electrode is segmented into two separate gates: a first gate electrode for controlling charge injection and a second gate electrode for controlling channel conduction. This segmentation enables independent optimization of each gate's function, achieving linear drain current response while maintaining fabrication feasibility through existing nanosheet transistor processes.
2Adaptability or versatility
If MMT devices are fabricated using existing nanosheet transistor processes, then integration is achieved, but performance requirements and cost constraints may not be met
Solution Approach 1:
The patent designs MMT devices that can be fabricated using the same nanosheet transistor process flow, making the fabrication process universal. The same tools, materials, and process steps used for nanosheet transistors are applied to MMT devices, enabling integration while meeting performance requirements through proper device design and characterization.
3Adaptability or versatility
If MMT devices with separate gates are fabricated, then linear drain current response is achieved, but fabrication complexity increases
Solution Approach 1:
The patent merges the fabrication of MMT devices with existing nanosheet transistor fabrication processes. By combining the same process steps for both device types and using shared materials and tools, the overall fabrication complexity is reduced despite the additional MMT device elements being introduced.
Data Source
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AI summary
A semiconductor device and fabrication method are described for integrating a nanosheet transistor with a multimodal transistor (MMT) in a single nanosheet process flow by processing a wafer substrate to form buried metal source/drain structures in an MMT region that are laterally spaced apart from one another and positioned below an MMT semiconductor channel layer before forming a transistor stack of alternating Si and SiGe layers in an FET region which are selectively processed to form gate electrode openings so that a first ALD oxide and metal layer are patterned and etched to form gate electrodes in the transistor stack and to form a channel control gate electrode over the MMT semiconductor channel layer, and so that a second oxide and conductive layer are patterned and etched to form a current control gate electrode over the MMT semiconductor channel layer and adjacent to the channel control gate electrode.