Multi-Modulus Divider Bypass Control for Continuous Division Range
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Solution Overview
Problem
Current multi-modulus dividers face limitations in achieving accurate frequency division across a wide range, especially when the divisor value hops from less than 2K to greater than or equal to 2K, leading to errors in fractional-N frequency synthesizers, resulting in phase noise and out-of-lock issues.
Innovation Solution
A multi-modulus divider with a pulse generating circuit and a modulus signal generating circuit that determines the numerical interval of the divisor, inputting a pulse signal to the appropriate divider cell to ensure correct loading, thereby generating a pseudo-modulus signal for accurate frequency division across a continuous range.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If bypassing logic circuits are added to extend division range, then the division range is extended, but division errors occur when divisor hops from less than 2K to greater than or equal to 2K
Solution Approach 1:
The patent applies preliminary action by generating a pulse signal in advance when the divisor value changes from less than 2K to greater than or equal to 2K. This pulse signal is sent to the bypassing logic circuit before the division operation completes, ensuring the circuit configuration is updated proactively. This prevents division errors by preparing the bypassing logic ahead of time rather than reactively, maintaining both extended division range and high division accuracy.
2Adaptability or versatility
If more divider cells are used to increase division range, then the division range increases, but the device complexity increases
Solution Approach 1:
The patent applies dynamics by making the bypassing logic circuits controllable and reconfigurable based on the divisor value. Instead of having fixed, static bypassing paths, the circuit dynamically adjusts which divider cells are bypassed and which are active, controlled by the pulse signal generated from the divisor value detection. This dynamic configuration allows the circuit to maintain optimal performance across different division ranges without requiring a permanently complex fixed structure.
3Adaptability or versatility
If bypassing logic circuits are added to extend division range, then the division range is extended, but phase noise is generated
Solution Approach 1:
The patent applies feedback by continuously monitoring the divisor value and using this information to control the bypassing logic circuits. The pulse signal generation is based on feedback from the divisor value comparison (detecting when it transitions from less than 2K to greater than or equal to 2K). This closed-loop feedback mechanism ensures that bypassing is activated only when necessary and controlled precisely, preventing the uncontrolled switching that would generate phase noise while maintaining the extended division range capability.
Data Source
AI summary
A multi-modulus divider and a method for performing frequency dividing by utilizing a multi-modulus divider are disclosed. The multi-modulus divider comprises a multi-modulus dividing circuit, a pulse generating circuit, and a modulus signal generating circuit. The multi-modulus dividing circuit comprises several serially connected divider cells, of which a predetermined one may be bypassed. The multi-modulus dividing circuit generates an output frequency according to an input frequency and a divisor. A range of the divisor comprises a plurality of numerical intervals. The pulse generating circuit generates a pulse signal. The modulus signal generating circuit generates a determination result by determining which numerical interval the divisor belongs to, and inputs, according to the determination result, the pulse signal into the predetermined divider cell to be one of references which the predetermined divider cell refers to when outputting a modulus signal. The predetermined divider cell corresponds to the determination result.