Multi-path peaking technique for equalization and supply noise compensation
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Solution Overview
Problem
High-speed data transmission in modern applications like deep machine learning and GPU applications faces significant channel loss due to inter-symbol interference and severe supply noise, requiring complex and power-consuming equalization techniques.
Innovation Solution
A multi-path receiver circuit with stages comprising MOSFETs, where the input signal is shared among transistor inputs, maintaining constant DC gain while accumulating AC gain across stages, providing greater equalization capability and peaking gain at higher frequencies.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional equalization techniques (transmitter pre-emphasis, multi-stage receiver CTLE, multi-tap receiver DFE) are used to compensate channel loss at 12.5 GHz, then the bit error rate can be maintained at -12, but power consumption and design complexity increase significantly
Solution Approach 1:
The receiver circuit is divided into multiple stages, each contributing to the overall equalization function. The multi-stage architecture segments the signal processing task across several amplifier stages, allowing distributed equalization without requiring a single complex equalizer stage
Solution Approach 2:
The multi-stage receiver circuit performs multiple functions simultaneously: it provides signal amplification, equalization, and supply noise rejection all within a unified circuit architecture, eliminating the need for separate dedicated equalization circuits
2Reliability
If conventional equalization techniques are used to compensate channel loss at 12.5 GHz, then the bit error rate can be maintained at -12, but power consumption increases
Solution Approach 1:
The circuit employs dynamic biasing and frequency-dependent gain control to optimize power efficiency. The multi-stage architecture allows each stage to operate at optimized bias points, and the circuit dynamically adjusts its response based on the frequency content of the input signal
Solution Approach 2:
The circuit converts the harmful effect of supply noise into a beneficial filtering mechanism. By designing the multi-stage circuit with specific pole-zero placements, the natural resonances and frequency responses of the circuit stages work together to reject supply noise while maintaining signal integrity
3Speed
If the channel loss is compensated using all available equalization schemes, then data can be transmitted at 25 Gbps with acceptable bit error rate, but the accumulated loss requires additional equalization capacity increasing complexity
Solution Approach 1:
The patent transitions from traditional single-stage equalization to a multi-dimensional multi-stage approach. Each stage adds a new dimension to the equalization capability, with stages cascaded to provide cumulative equalization effect without linearly increasing the complexity of individual stages
Data Source
AI summary
A multi-stage amplifier circuit equalizes an input signal through multiple signal amplification paths. DC gain is kept substantially constant over frequency, while adjustable high-frequency gain provides equalization (e.g., peaking). Various embodiments include a common source topology, a common gate topology, differential signaling topologies, and a topology suitable for stabilizing a voltage supply against high-frequency transient loads. A system may include one or more integrated circuits that may each include one or more instances of the multi-stage amplifier.