Multi-Phase Clock Divider Using Zero-Count Counter Architecture
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Solution Overview
Problem
Existing clock divider circuits require significant integrated circuit surface area and complexity to handle multiple clock frequencies, particularly when dividing multi-phase clock signals, leading to increased complexity and area usage.
Innovation Solution
A clock divider circuit that receives multiple input clock signals of the same frequency, each with a phase offset, and divides their frequency by an integer factor using a counter and flip-flops, achieving minimal circuit complexity and surface area by generating multiple equidistant clock phases of different frequencies.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If separate clock generators are used for various required clock frequencies, then each clock signal can be generated independently, but the area and complexity of the clock generator module increases
Solution Approach 1:
A single clock generator produces a high-frequency clock signal that serves as the source for multiple different clock frequencies. The clock divider circuit divides this single input clock signal into multiple output clock signals with different frequencies (f/K1, f/K2, f/K3), allowing one generator to perform the work of multiple generators.
Solution Approach 2:
The clock division function is segmented into multiple independent divider circuits, each handling a specific frequency division ratio. This allows the system to maintain a single compact clock generator while distributing the frequency conversion tasks across separate division stages.
2Area of stationary object
If a single clock generator provides the highest frequency clock signal, then the generator area is minimized, but additional clock dividers are required to obtain lower frequency clock signals
Solution Approach 1:
Multiple clock division functions are merged into a single integrated clock divider module. The circuit combines several division stages with different division ratios (K1, K2, K3) into one unified structure that accepts a single high-frequency clock input and produces multiple lower-frequency clock outputs simultaneously.
Solution Approach 2:
The clock divider circuit is designed to perform multiple frequency division operations in parallel, providing a universal solution that replaces what would otherwise require multiple separate divider circuits, thereby reducing overall system complexity.
3Productivity
If traditional clock dividers are used to divide multi-phase clock signals, then frequency division is achieved, but the circuit complexity and surface area increase significantly
Solution Approach 1:
Each phase of the multi-phase clock signal is processed independently through dedicated flip-flop stages within the divider circuit. The circuit maintains the phase relationships by applying local division operations to each phase input, preserving the equidistant phase characteristics in the outputs.
Solution Approach 2:
The clock divider uses identical flip-flop and counter circuit structures for each phase input, creating replicated division pathways. This modular copying approach simplifies the design by using the same proven circuit template multiple times rather than designing complex custom logic for each phase.
Data Source
AI summary
A clock divider circuit. The clock divider receives m input clock signals each of the same frequency. Each input clock signal after the first has a phase offset of 2π/m from the previous input clock signal. The clock divider divides the frequency of the input clock signals by an integer of division K. The clock divider includes a counter that receives the first input clock signal and provides one or more count signals. The clock divider also includes m flip-flops, of which a first flip-flop receives the first input clock signal at its clock input and provides a first clock output signal. Each flip-flop after the first receives an input clock signal at its clock input and provides a clock output signal, each clock output signal after the first having a 2πK/m phase offset from the previous clock output signal.