Multi-Phase Clock Divider Circuit With Reduced Area and Complexity
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Solution Overview
Problem
Existing clock divider circuits require significant integrated circuit surface area and complexity to generate multiple clock frequencies, especially when dividing multi-phase clock signals, leading to increased complexity and area usage.
Innovation Solution
A clock divider circuit that receives multiple input clock signals of the same frequency, with each signal having a phase offset, and uses a counter and flip-flops to divide the frequency by an integer factor, generating output clock signals with specific phase offsets, thereby reducing circuit complexity and area usage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If separate clock generators are used for various required clock frequencies, then each clock signal can be generated independently, but the area and complexity of the clock generator module increases
Solution Approach 1:
A single clock generator module generates multiple clock frequencies by combining a phase-locked loop (PLL) with programmable clock dividers. The PLL produces a high-frequency clock signal that is then divided by programmable dividers to generate multiple lower-frequency clock signals simultaneously, allowing one module to perform the function of multiple separate generators.
Solution Approach 2:
The clock generation system is segmented into functional blocks: a PLL section for high-frequency generation and multiple programmable clock divider sections for frequency multiplication and distribution. Each divider can be independently programmed to generate different clock frequencies, enabling flexible multi-frequency output from a unified generator.
2Area of stationary object
If a single clock generator is used to provide the highest frequency clock signal, then area is reduced, but additional clock divider circuits are required to obtain lower frequency clock signals
Solution Approach 1:
The programmable clock divider is designed to simultaneously perform multiple functions: frequency division, phase shifting, and distribution to multiple outputs. By integrating these functions into a single programmable unit, the system reduces the need for separate dedicated divider circuits for each frequency requirement.
Solution Approach 2:
The clock divider uses programmable division ratios that can be dynamically adjusted through control signals. This allows the same hardware circuit to adapt to different frequency requirements without requiring physical reconfiguration or multiple fixed-function dividers, thereby reducing overall circuit complexity.
3Speed
If traditional clock divider circuits are used to divide multi-phase clock signals, then frequency division is achieved, but circuit complexity and surface area increase
Solution Approach 1:
The patent uses replicated instances of a basic divider circuit block, where each instance handles a specific phase of the multi-phase clock signal. By copying a simple, standardized divider unit multiple times and connecting them in a systematic arrangement, the system achieves complex multi-phase frequency division without requiring a monolithic complex circuit.
Solution Approach 2:
The clock division architecture nests multiple division stages within a hierarchical structure. The PLL output feeds into first-stage dividers, whose outputs feed into second-stage dividers, creating a nested arrangement where simpler circuits are embedded within a larger systematic framework, reducing overall complexity compared to a flat implementation.
Data Source
AI summary
A clock divider circuit. The clock divider receives m input clock signals each of the same frequency. Each input clock signal after the first has a phase offset of 2π/m from the previous input clock signal. The clock divider divides the frequency of the input clock signals by an integer of division K. The clock divider includes a counter that receives the first input clock signal and provides one or more count signals. The clock divider also includes m flip-flops, of which a first flip-flop receives the first input clock signal at its clock input and provides a first clock output signal. Each flip-flop after the first receives an input clock signal at its clock input and provides a clock output signal, each clock output signal after the first having a 2πK/m phase offset from the previous clock output signal.