Multiphase Fractional Clock Divider for Low-Jitter PLL Synthesis
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Solution Overview
Problem
Fractional frequency synthesizers in phase-locked loop circuits suffer from performance limitations due to clock jitter, which degrades timing precision and signal quality, and this jitter can propagate across multiple system components, potentially leading to failure.
Innovation Solution
A frequency synthesizer circuit using a multiphase divider with a delta-sigma modulator to reduce quantization noise and increase PLL bandwidth, incorporating a ring oscillator for phase shifting and a pulse extension logic to smooth phase transitions, thereby reducing jitter and improving signal quality.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If a fractional multiplication factor is used in a frequency synthesizer, then the ability to generate non-integer multiples of reference frequency is improved, but clock jitter increases and timing precision deteriorates
Solution Approach 1:
The frequency synthesizer is divided into multiple integer-N PLLs operating in parallel, each generating an integer multiple of the reference frequency. A multiplexer then selects and combines these integer outputs to achieve fractional multiplication, thereby avoiding the jitter problems of direct fractional-N PLLs while maintaining frequency versatility.
Solution Approach 2:
A multiplexer is introduced as an intermediary component between the integer-N PLLs and the output. This multiplexer selects from multiple integer frequency outputs based on control signals, enabling fractional frequency synthesis without directly using fractional multiplication, thus preserving timing precision while achieving frequency adaptability.
2Reliability
If the PLL bandwidth is increased to reduce oscillator noise, then signal quality improves, but quantization noise from the sigma-delta modulator increases
Solution Approach 1:
The single PLL is segmented into multiple parallel integer-N PLLs. Each PLL processes a portion of the frequency synthesis task independently, allowing the use of wider bandwidth filters in each individual PLL without amplifying quantization noise from a single sigma-delta modulator, thereby improving signal quality while controlling noise.
Solution Approach 2:
The sigma-delta modulator and its associated quantization noise are extracted from the core PLL loop. By using integer-N PLLs with a multiplexer, the system eliminates the need for a sigma-delta modulator in the feedback path, removing the source of quantization noise while maintaining the ability to generate fractional frequencies.
3Adaptability or versatility
If multiple integer-N PLLs are cascaded to achieve fractional multiplication, then frequency versatility is improved, but device complexity increases
Solution Approach 1:
Multiple integer-N PLLs are merged into a single integrated frequency synthesizer block with a common reference clock and shared output infrastructure. This combining approach achieves the frequency versatility of cascaded PLLs while reducing overall complexity through resource sharing and integrated control logic.
Solution Approach 2:
The frequency synthesizer is designed as a universal module that can generate multiple frequency outputs simultaneously. By making the PLL circuitry multi-functional capable of producing various integer multiples of the reference frequency, the system eliminates the need for separate dedicated PLL circuits for each frequency, thereby reducing device complexity while maintaining versatility.
Data Source
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AI summary
An oscillator provides a plurality of clock signals, including a first clock signal having a first frequency and a first period, wherein each clock signal has the first frequency and is phase shifted from the first clock signal by an integer times a predetermined fractional amount of the first period. A multiphase frequency divider receives the plurality of clock signals and provides a divided clock output, and includes an integer frequency divider which provides the divided clock output based on a modified clock input and a clock selector which provides a current clock as the modified clock input during a first portion of the divided clock output and a next clock as the modified clock input during a subsequent portion of the divided clock output. The next clock is selected from the plurality of clock signals based on a selected fractional phase shift amount indicated by a sigma-delta modulator.