Multi-Phase Clock Error Detection Using Interval Signals
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Solution Overview
Problem
Current error detection methods in semiconductor devices face challenges in accurately generating and utilizing multi-phase signals to detect errors in clock signals, leading to inefficiencies and potential distortions due to PVT variations and mismatches in resistance between level shifters and low-pass filters.
Innovation Solution
The implementation of an error detector that generates interval signals from phase signals and uses low-pass filters and comparators to determine errors, with delay cells adjusting duty ratios or phases to correct errors, thereby maintaining phase differences and reducing distortion.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If multi-phase clock signals are generated and used for error detection, then error detection capability is improved, but circuit complexity increases due to PVT variations and resistance mismatches
Solution Approach 1:
The error detection function is segmented into multiple independent error detectors, each dedicated to detecting errors in specific phase signals. This segmentation allows parallel processing of multiple phases while maintaining modular design, reducing the overall circuit complexity compared to a monolithic error detection system.
Solution Approach 2:
Interval signals are introduced as intermediary elements that facilitate error detection by representing phase relationships in a simplified form. These interval signals serve as mediators between the complex multi-phase clock signals and the error detection logic, making the detection process more manageable and less susceptible to PVT variations.
2Measurement precision
If level shifters and low-pass filters are used in error detection circuits, then measurement precision is improved, but manufacturing precision deteriorates due to resistance mismatches
Solution Approach 1:
The invention changes the operational parameters of the error detection circuit by using interval signals with standardized time intervals. This parameter change allows the circuit to operate in a regime where precise resistance matching is less critical, as the error detection is based on time interval comparisons rather than voltage level comparisons that are sensitive to resistance variations.
Solution Approach 2:
Multiple error detectors are designed with identical circuit structures that are replicated for different phase signals. This copying approach ensures that all detectors experience the same PVT variations and resistance characteristics, allowing for consistent error detection across all phases without requiring precise individual matching of each component.
3Reliability
If delay cells are added to correct phase errors, then reliability is improved, but device complexity increases
Solution Approach 1:
Delay cells are configured to provide preliminary phase adjustment before the corrected signals are used in subsequent operations. By pre-correcting phase errors in a controlled manner, the system maintains high reliability without requiring complex real-time adjustment mechanisms, thus balancing reliability improvement with circuit simplicity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution effectively detects and corrects errors in multi-phase clock signals, improving the accuracy and reliability of semiconductor device operations by maintaining precise phase differences and reducing the size and complexity of error correction circuits.
Implementation Method 1
a first low-pass filter configured to convert the first interval signal to a first voltage and converting the second interval signal to a second voltage
Data Source
AI summary
An error detector includes a first pulse generator configured to generate first and second interval signals in response to a plurality of phase signals, a first low-pass filter configured to convert the first and second interval signals into respective first and second voltages, and a first comparator configured to determine an error in a first phase signal among the plurality of phase signals, in response to the first and second voltages. The first pulse generator may be configured to generate the first interval signal in response to the first phase signal and a second phase signal among the plurality of phase signals, and generate the second interval signal in response to the first phase signal and a third phase signal among the plurality of phase signals.