Multi-Phase Clock Gating with Phase Selection for Fast Resynchronization
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Solution Overview
Problem
Synchronous circuits face challenges in synchronizing with exact clock edges after re-initialization due to phase drift caused by temperature, voltage changes, and other conditions, leading to time-consuming re-initialization processes and loss of prior phase adjustments.
Innovation Solution
A multi-phase clock gater circuit with phase selection capabilities, allowing selective start and stop phases for clock gating, and a loop control circuit to manage phase drift across rotations, ensuring synchronized clock signals without lengthy synchronization processes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If clock gating is implemented to save power when synchronous circuit is not needed, then power consumption is reduced, but the circuit requires time-consuming re-initialization and synchronization when restarted
Solution Approach 1:
The patent applies preliminary action by maintaining the clock signal in a held state rather than completely gating it off. The multi-phase clock gater circuit preserves the phase relationships and keeps the clock signal ready, so when the synchronous circuit needs to restart, no re-initialization is required. The clock signal is already prepared in the correct phase state, eliminating the time-consuming synchronization process while still achieving power savings during idle periods.
2Loss of energy
If traditional clock gating is used to stop clock signals during idle periods, then power consumption decreases, but phase drift occurs and prior phase adjustments are lost upon re-initialization
Solution Approach 1:
The patent applies preliminary action by maintaining the clock signal in a held state rather than completely gating it off. The multi-phase clock gater circuit preserves the phase relationships and keeps the clock signal ready, so when the synchronous circuit needs to restart, no re-initialization is required. The clock signal is already prepared in the correct phase state, eliminating the time-consuming synchronization process while still achieving power savings during idle periods.
Solution Approach 2:
The patent applies continuity of useful action by keeping the clock signal continuously available in a held state rather than interrupting it completely. The multi-phase clock gater maintains the clock signal's phase relationships and continuity, ensuring that when the synchronous circuit resumes operation, the clock is already synchronized and ready. This continuous availability prevents phase drift and maintains reliability while still reducing power consumption during idle periods.
3Device complexity
If multi-phase clock signal is gated without phase selection, then circuit complexity is reduced, but the circuit cannot track phase drift or maintain phase adjustments during gating
Solution Approach 1:
The patent applies segmentation by dividing the clock signal into multiple phases (e.g., four phases) and providing separate control for each phase through the multi-phase clock gater circuit. Each phase can be independently gated or held, allowing the circuit to track phase drift by maintaining appropriate phase relationships. This segmentation enables phase tracking capability while keeping the overall circuit structure manageable through systematic organization of the gater logic.
Solution Approach 2:
The patent applies dynamics by making the clock gater circuit adjustable and adaptable through phase selection inputs. The circuit can dynamically select which phase to hold or gate based on operational requirements, enabling it to track phase drift and maintain phase adjustments. This dynamic capability allows the circuit to adapt to changing conditions while maintaining a relatively simple underlying structure, resolving the contradiction between complexity and adaptability.
Data Source
AI summary
A multi-phase clock gating circuit receives a plurality of respective phased clock signals, and a one-hot stop phase select signal indicating a first selected phase for which gating of the phased clock signals is to be started. Responsive to a clock control signal indicating the phased clock signals are to be gated, the clock signals are gated beginning at the first selected phase, in order of phase, including looping from a last phase to a first phase.