Multi-Phase Frequency Divider With Latch-Stabilized Ring Inverters
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Solution Overview
Problem
Existing technologies face challenges in generating odd-numbered multiphase clocks with equally spaced phases, as odd numbers of inverters in ring oscillators do not produce a total phase shift of 360 degrees, limiting the generation of such clocks.
Innovation Solution
A multi-phase digital frequency divider is designed using dynamic inverters connected in a ring with stabilized intermediate nodes by cross-coupled latches, allowing for the generation of multiphase clocks by dividing an input clock signal by any even integer, utilizing a minimal number of transistors and enabling expansion to produce evenly distributed phases.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If ring oscillators with even numbers of inverters are used, then even-numbered multiphase clocks can be generated, but odd-numbered multiphase clocks cannot be generated because the total phase shift around the loop is not 360 degrees
Solution Approach 1:
The patent divides the clock generation function into two separate modules: a ring oscillator that generates even-numbered multiphase clocks and a frequency divider that converts them to odd-numbered multiphase clocks. This segmentation allows each module to operate optimally while achieving the overall goal of generating odd-numbered phases.
Solution Approach 2:
The patent introduces an intermediate even-numbered multiphase clock signal as a mediator between the ring oscillator and the desired odd-numbered multiphase clock. The frequency divider uses this intermediate signal to synthesize the final odd-numbered phases through combinatorial logic.
2Adaptability or versatility
If traditional frequency dividers are used to generate odd-numbered multiphase clocks, then odd-numbered phases can be produced, but the number of transistors required increases significantly
Solution Approach 1:
The patent merges the generation of multiple phase signals by combining outputs from the ring oscillator through shared combinatorial logic circuits. Instead of generating each phase independently, the design reuses common signal paths and logic gates to produce multiple phases from a single even-numbered multiphase source.
Solution Approach 2:
The frequency divider circuit is designed to be universally applicable for generating any odd-numbered multiphase clock by configuring the combinatorial logic. The same basic circuit structure can be adapted to generate 3-phase, 5-phase, 7-phase, or any other odd-numbered multiphase clock by changing the logic configuration rather than redesigning the entire circuit.
Data Source
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AI summary
A multi-phase frequency divider comprises dynamic inverters connected in a ring and the intermediate nodes around the ring are stabilized with cross-coupled latches. Clock input pulses enable each dynamic inverter's output and will force a corresponding change- of-state in the cross-coupled latches. The multi-phase output is presented in parallel on all the latches.