Multiphase PLL Transmitter for Higher Wireless Data Rates
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing wireless communication systems face challenges in increasing the data rate of data signals for improved throughput.
Innovation Solution
A transmitter is designed with a phase locked loop (PLL) that includes a multiphase oscillator generating clock signals with different phases, a multiplexer selecting between these clock signals, and a power amplifier amplifying data signals based on these clock signals, thereby enhancing data transmission efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If a single clock signal is used in the transmitter, then the device complexity is low, but the data rate is limited
Solution Approach 1:
The single clock signal is segmented into multiple phase-shifted clock signals (e.g., 0°, 90°, 180°, 270°) using a phase shifter. This segmentation allows parallel processing of multiple data streams, thereby increasing the data rate without proportionally increasing the overall system complexity.
Solution Approach 2:
The invention transitions from a single-dimensional time-based data transmission to a multi-dimensional approach by introducing phase as an additional dimension. Multiple data streams are transmitted simultaneously on the same frequency but with different phases, effectively increasing the data rate by utilizing the phase dimension.
2Productivity
If multiple clock signals with different phases are generated, then the data rate increases, but the device complexity increases
Solution Approach 1:
The phase shifter is designed as a universal component that can generate multiple phase-shifted clock signals from a single input clock signal. This multi-functional component reduces the need for separate clock generators for each phase, thereby increasing data rate while minimizing the increase in device complexity.
Solution Approach 2:
The phase-shifting operation is performed in advance on the clock signal before it is distributed to multiple modulators. This preliminary action ensures that all phase-shifted clock signals are readily available for parallel data modulation, increasing data rate without requiring complex real-time phase management.
3Productivity
If parallel modulation paths are used, then the throughput is improved, but the manufacturing precision requirements increase
Solution Approach 1:
The invention incorporates feedback mechanisms that monitor and adjust the phase relationships between multiple clock signals. This feedback ensures that phase alignment is maintained despite manufacturing variations, allowing parallel modulation paths to achieve high throughput without requiring extremely tight manufacturing precision.
Data Source
AI summary
This disclosure is directed to a transmitter including a phase locked loop (PLL), a modulator, and a power amplifier (PA). A controller including programmable and/or hardened logic circuitry may be coupled to the PLL and the modulator. The controller may provide encoded signals based on quadrature phase shift keying (QPSK) scheme for transmission by the transmitter. In particular, the controller may provide multiple bursts of pulses indicative of data packets to the modulator. Moreover, the controller may provide instructions indicative of generating clock signals with in-phase and quadrature phases to the PLL. The PLL may generate clock signals corresponding to the in-phase and quadrature phases. As such, the transmitter may generate in-phase and quadrature output signals based on receiving each burst of pulses with either in-phase or quadrature phases.