Multiphase PWM Signal Generation for Fine Duty Cycle Control
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Solution Overview
Problem
Existing PWM signal generation methods face limitations in achieving high resolution and precision due to clock frequency constraints, leading to inaccuracies in controlling voltage and current in applications like wireless battery chargers and motor control, which require precise duty cycle adjustments to minimize power consumption and noise.
Innovation Solution
A PWM signal generator circuit utilizing a multiphase clock generator to generate phase-shifted clock phases, combined with a timer circuit and phase accumulator, allows for precise control of switch-on and switch-off durations by adjusting clock phases to achieve high resolution PWM signals.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If a digital implementation using a clock signal and counter is used to generate PWM signal, then the circuit structure is simple, but the accuracy and resolution of the PWM signal is limited by the clock period
Solution Approach 1:
The invention segments the clock period into multiple phases by generating multiple phase-shifted clock signals (e.g., 4 phases with 90-degree shifts). This allows the PWM duty cycle to be controlled with finer granularity by selecting different phase combinations, thereby improving resolution without requiring a higher clock frequency or more complex digital logic.
Solution Approach 2:
The invention transitions from a single-dimension time-based counting approach to a multi-dimensional phase-based approach. By introducing multiple clock phases as an additional dimension, the system can achieve higher resolution PWM control through phase combination selection rather than relying solely on increasing clock frequency or counter precision.
2Measurement precision
If the clock frequency is increased to improve PWM signal resolution, then the accuracy and resolution of the PWM signal improves, but the switching losses increase
Solution Approach 1:
The invention changes the parameter used for PWM resolution from clock frequency to clock phase number. Instead of increasing fCLK, the system increases the number of phase steps (e.g., from 1 phase to 4 phases), allowing fine-grained duty cycle control while maintaining the same clock frequency and avoiding increased switching losses.
Solution Approach 2:
The invention introduces dynamic phase selection where different phase combinations are selected based on the required PWM duty cycle. This dynamic switching between phase combinations allows precise control of the effective switching timing without requiring the actual switching frequency to increase, thereby maintaining low switching losses.
3Measurement precision
If multiple clock phases are generated via Delay Locked Loop to achieve high resolution PWM, then the PWM signal resolution improves, but the device complexity increases
Solution Approach 1:
The invention extracts only the essential function of phase generation from the complex DLL circuit. Instead of implementing a full DLL with phase detectors, charge pumps, and loop filters, the patent uses a simplified phase shift network that directly generates the required phase-shifted clock signals, significantly reducing circuit complexity while maintaining the phase-based high resolution PWM capability.
4Volume of moving object
If a half-bridge or full bridge is used to drive resonant tank at high frequency, then the equipment size is reduced, but the requirement for high-frequency modulated waveform PWM signal with high precise resolution increases
Solution Approach 1:
The invention segments the high-frequency switching control into multiple phase steps, allowing precise duty cycle adjustment even at high switching frequencies. This enables the resonant tank to operate at high frequency (reducing equipment size) while the PWM control maintains high resolution through phase-based timing control.
Data Source
AI summary
A PWM signal generator circuit includes a multiphase clock generator that generates a number n of phase-shifted clock phases having the same clock period and being phase shifted by a time corresponding to a fraction 1/n of the clock period. The PWM signal generator circuit determines for each switch-on duration first and second integer numbers, and for each switch-off duration third and fourth integer numbers. The first integer number is indicative of the integer number of clock periods of the switch-on duration and the second integer number is indicative of the integer number of the additional fractions 1/n of the clock period of the switch-on duration. The third integer number is indicative of the integer number of clock periods of the switch-off duration, and the fourth integer number is indicative of the integer number of the additional fractions 1/n of the clock period of the switch-off duration.